LLVM 20.0.0git
MachineCycleAnalysis.cpp
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1//===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
16
17using namespace llvm;
18
21
23
27}
28
30 "Machine Cycle Info Analysis", true, true)
33
34void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
35 AU.setPreservesAll();
37}
38
40 CI.clear();
41
42 F = &Func;
43 CI.compute(Func);
44 return false;
45}
46
48 OS << "MachineCycleInfo for function: " << F->getName() << "\n";
49 CI.print(OS);
50}
51
53 CI.clear();
54 F = nullptr;
55}
56
57namespace {
58class MachineCycleInfoPrinterPass : public MachineFunctionPass {
59public:
60 static char ID;
61
62 MachineCycleInfoPrinterPass();
63
64 bool runOnMachineFunction(MachineFunction &F) override;
65 void getAnalysisUsage(AnalysisUsage &AU) const override;
66};
67} // namespace
68
69char MachineCycleInfoPrinterPass::ID = 0;
70
71MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass()
74}
75
76INITIALIZE_PASS_BEGIN(MachineCycleInfoPrinterPass, "print-machine-cycles",
77 "Print Machine Cycle Info Analysis", true, true)
79INITIALIZE_PASS_END(MachineCycleInfoPrinterPass, "print-machine-cycles",
80 "Print Machine Cycle Info Analysis", true, true)
81
82void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const {
83 AU.setPreservesAll();
84 AU.addRequired<MachineCycleInfoWrapperPass>();
86}
87
88bool MachineCycleInfoPrinterPass::runOnMachineFunction(MachineFunction &F) {
89 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
90 CI.print(errs());
91 return false;
92}
93
95 MachineFunction *MF = I.getParent()->getParent();
97 const TargetSubtargetInfo &ST = MF->getSubtarget();
98 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
99 const TargetInstrInfo *TII = ST.getInstrInfo();
100
101 // The instruction is cycle invariant if all of its operands are.
102 for (const MachineOperand &MO : I.operands()) {
103 if (!MO.isReg())
104 continue;
105
106 Register Reg = MO.getReg();
107 if (Reg == 0)
108 continue;
109
110 // An instruction that uses or defines a physical register can't e.g. be
111 // hoisted, so mark this as not invariant.
112 if (Reg.isPhysical()) {
113 if (MO.isUse()) {
114 // If the physreg has no defs anywhere, it's just an ambient register
115 // and we can freely move its uses. Alternatively, if it's allocatable,
116 // it could get allocated to something with a def during allocation.
117 // However, if the physreg is known to always be caller saved/restored
118 // then this use is safe to hoist.
119 if (!MRI->isConstantPhysReg(Reg) &&
120 !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
121 !TII->isIgnorableUse(MO))
122 return false;
123 // Otherwise it's safe to move.
124 continue;
125 } else if (!MO.isDead()) {
126 // A def that isn't dead can't be moved.
127 return false;
128 } else if (any_of(Cycle->getEntries(),
129 [&](const MachineBasicBlock *Block) {
130 return Block->isLiveIn(Reg);
131 })) {
132 // If the reg is live into any header of the cycle we can't hoist an
133 // instruction which would clobber it.
134 return false;
135 }
136 }
137
138 if (!MO.isUse())
139 continue;
140
141 assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
142
143 // If the cycle contains the definition of an operand, then the instruction
144 // isn't cycle invariant.
145 if (Cycle->contains(MRI->getVRegDef(Reg)->getParent()))
146 return false;
147 }
148
149 // If we got this far, the instruction is cycle invariant!
150 return true;
151}
unsigned const MachineRegisterInfo * MRI
basic Basic Alias true
block Block Frequency Analysis
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:371
cycles
This template implementation resides in a separate file so that it does not get injected into every ....
const HexagonInstrInfo * TII
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
This file declares a specialization of the GenericSSAContext<X> template class for Machine IR.
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:57
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
Represent the analysis usage information of a pass.
Cycle information for a function.
void print(raw_ostream &Out) const
Print the cycle info.
void clear()
Reset the object to its initial state.
void compute(FunctionT &F)
Compute the cycle info for a function.
A possibly irreducible generalization of a Loop.
const SmallVectorImpl< BlockT * > & getEntries() const
bool contains(const BlockT *Block) const
Return whether Block is contained in the cycle.
Legacy analysis pass which computes a MachineCycleInfo.
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
Definition: MachineInstr.h:69
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
TargetInstrInfo - Interface to description of machine instruction set.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I)
Printable print(const GCNRegPressure &RP, const GCNSubtarget *ST=nullptr)
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1729
MachineCycleInfo::CycleT MachineCycle
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void initializeMachineCycleInfoPrinterPassPass(PassRegistry &)