LLVM  16.0.0git
MachineCycleAnalysis.cpp
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1 //===- MachineCycleAnalysis.cpp - Compute CycleInfo for Machine IR --------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
14 
15 using namespace llvm;
16 
19 
21 
25 }
26 
28  "Machine Cycle Info Analysis", true, true)
30  "Machine Cycle Info Analysis", true, true)
31 
32 void MachineCycleInfoWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
33  AU.setPreservesAll();
35 }
36 
38  CI.clear();
39 
40  F = &Func;
41  CI.compute(Func);
42  return false;
43 }
44 
46  OS << "MachineCycleInfo for function: " << F->getName() << "\n";
47  CI.print(OS);
48 }
49 
51  CI.clear();
52  F = nullptr;
53 }
54 
56 public:
57  static char ID;
58 
60 
61  bool runOnMachineFunction(MachineFunction &F) override;
62  void getAnalysisUsage(AnalysisUsage &AU) const override;
63 };
64 
66 
69  initializeMachineCycleInfoPrinterPassPass(*PassRegistry::getPassRegistry());
70 }
71 
73  "Print Machine Cycle Info Analysis", true, true)
77 
78 void MachineCycleInfoPrinterPass::getAnalysisUsage(AnalysisUsage &AU) const {
79  AU.setPreservesAll();
80  AU.addRequired<MachineCycleInfoWrapperPass>();
81  MachineFunctionPass::getAnalysisUsage(AU);
82 }
83 
85  auto &CI = getAnalysis<MachineCycleInfoWrapperPass>();
86  CI.print(errs());
87  return false;
88 }
89 
91  MachineFunction *MF = I.getParent()->getParent();
93  const TargetSubtargetInfo &ST = MF->getSubtarget();
94  const TargetRegisterInfo *TRI = ST.getRegisterInfo();
95  const TargetInstrInfo *TII = ST.getInstrInfo();
96 
97  // The instruction is cycle invariant if all of its operands are.
98  for (const MachineOperand &MO : I.operands()) {
99  if (!MO.isReg())
100  continue;
101 
102  Register Reg = MO.getReg();
103  if (Reg == 0)
104  continue;
105 
106  // An instruction that uses or defines a physical register can't e.g. be
107  // hoisted, so mark this as not invariant.
108  if (Register::isPhysicalRegister(Reg)) {
109  if (MO.isUse()) {
110  // If the physreg has no defs anywhere, it's just an ambient register
111  // and we can freely move its uses. Alternatively, if it's allocatable,
112  // it could get allocated to something with a def during allocation.
113  // However, if the physreg is known to always be caller saved/restored
114  // then this use is safe to hoist.
115  if (!MRI->isConstantPhysReg(Reg) &&
116  !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())) &&
117  !TII->isIgnorableUse(MO))
118  return false;
119  // Otherwise it's safe to move.
120  continue;
121  } else if (!MO.isDead()) {
122  // A def that isn't dead can't be moved.
123  return false;
124  } else if (any_of(Cycle->getEntries(),
125  [&](const MachineBasicBlock *Block) {
126  return Block->isLiveIn(Reg);
127  })) {
128  // If the reg is live into any header of the cycle we can't hoist an
129  // instruction which would clobber it.
130  return false;
131  }
132  }
133 
134  if (!MO.isUse())
135  continue;
136 
137  assert(MRI->getVRegDef(Reg) && "Machine instr not mapped for this vreg?!");
138 
139  // If the cycle contains the definition of an operand, then the instruction
140  // isn't cycle invariant.
142  return false;
143  }
144 
145  // If we got this far, the instruction is cycle invariant!
146  return true;
147 }
cycles
machine cycles
Definition: MachineCycleAnalysis.cpp:29
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
llvm::MachineCycle
MachineCycleInfo::CycleT MachineCycle
Definition: MachineCycleAnalysis.h:28
print
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
Definition: ArchiveWriter.cpp:189
llvm::initializeMachineCycleInfoWrapperPassPass
void initializeMachineCycleInfoWrapperPassPass(PassRegistry &)
MachineCycleInfoPrinterPass::ID
static char ID
Definition: MachineCycleAnalysis.cpp:57
llvm::MachineRegisterInfo
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Definition: MachineRegisterInfo.h:50
llvm::X86Disassembler::Reg
Reg
All possible values of the reg field in the ModR/M byte.
Definition: X86DisassemblerDecoder.h:462
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition: MachineFunctionPass.h:30
llvm::TargetRegisterInfo
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
Definition: TargetRegisterInfo.h:236
TargetInstrInfo.h
llvm::errs
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
Definition: raw_ostream.cpp:891
llvm::MachineCycleInfoWrapperPass::MachineCycleInfoWrapperPass
MachineCycleInfoWrapperPass()
Definition: MachineCycleAnalysis.cpp:22
TRI
unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1628
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:167
F
#define F(x, y, z)
Definition: MD5.cpp:55
MachineRegisterInfo.h
llvm::MachineCycleInfoWrapperPass::releaseMemory
void releaseMemory() override
releaseMemory() - This member can be implemented by a pass if it wants to be able to release its memo...
Definition: MachineCycleAnalysis.cpp:50
llvm::MachineFunction::getRegInfo
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:667
llvm::TargetInstrInfo
TargetInstrInfo - Interface to description of machine instruction set.
Definition: TargetInstrInfo.h:98
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition: PassAnalysisSupport.h:47
llvm::isCycleInvariant
bool isCycleInvariant(const MachineCycle *Cycle, MachineInstr &I)
Definition: MachineCycleAnalysis.cpp:90
TII
const HexagonInstrInfo * TII
Definition: HexagonCopyToCombine.cpp:125
Analysis
machine Machine Cycle Info Analysis
Definition: MachineCycleAnalysis.cpp:30
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition: MachineOperand.h:48
llvm::GenericCycle
A possibly irreducible generalization of a Loop.
Definition: GenericCycleInfo.h:48
llvm::raw_ostream
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:53
Info
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
llvm::MachineRegisterInfo::getVRegDef
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
Definition: MachineRegisterInfo.cpp:396
llvm::TargetRegisterInfo::isCallerPreservedPhysReg
virtual bool isCallerPreservedPhysReg(MCRegister PhysReg, const MachineFunction &MF) const
Physical registers that may be modified within a function but are guaranteed to be restored before an...
Definition: TargetRegisterInfo.h:565
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
llvm::MachineBasicBlock
Definition: MachineBasicBlock.h:94
llvm::MachineCycleInfoWrapperPass::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineCycleAnalysis.cpp:37
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::GenericCycleInfo::compute
void compute(FunctionT &F)
Compute the cycle info for a function.
Definition: GenericCycleImpl.h:356
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition: MachineFunction.h:657
llvm::MachineInstr
Representation of each machine instruction.
Definition: MachineInstr.h:66
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
MachineCycleInfoPrinterPass::MachineCycleInfoPrinterPass
MachineCycleInfoPrinterPass()
Definition: MachineCycleAnalysis.cpp:67
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::GenericCycle::getEntries
const SmallVectorImpl< BlockT * > & getEntries() const
Definition: GenericCycleInfo.h:103
llvm::MachineFunction::getName
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
Definition: MachineFunction.cpp:567
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
MachineCycleInfoPrinterPass
Definition: MachineCycleAnalysis.cpp:55
llvm::MachineCycleInfoWrapperPass::print
void print(raw_ostream &OS, const Module *M=nullptr) const override
print - Print out the internal state of the pass.
Definition: MachineCycleAnalysis.cpp:45
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::GenericCycleInfo
Cycle information for a function.
Definition: GenericCycleInfo.h:44
llvm::any_of
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1741
llvm::rdf::Print
Print(const T &, const DataFlowGraph &) -> Print< T >
TargetSubtargetInfo.h
llvm::MachineInstr::getParent
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:313
llvm::TargetSubtargetInfo
TargetSubtargetInfo - Generic base class for all target subtargets.
Definition: TargetSubtargetInfo.h:62
MRI
unsigned const MachineRegisterInfo * MRI
Definition: AArch64AdvSIMDScalarPass.cpp:105
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::MachineRegisterInfo::isConstantPhysReg
bool isConstantPhysReg(MCRegister PhysReg) const
Returns true if PhysReg is unallocatable and constant throughout the function.
Definition: MachineRegisterInfo.cpp:515
MachineCycleAnalysis.h
llvm::GenericCycleInfo::print
void print(raw_ostream &Out) const
Print the cycle info.
Definition: GenericCycleImpl.h:462
MachineCycleInfoPrinterPass::runOnMachineFunction
bool runOnMachineFunction(MachineFunction &F) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Definition: MachineCycleAnalysis.cpp:84
llvm::GenericCycleInfo::clear
void clear()
Reset the object to its initial state.
Definition: GenericCycleImpl.h:348
llvm::MachineCycleInfoWrapperPass::ID
static char ID
Definition: MachineCycleAnalysis.h:36
llvm::MachineCycleInfoWrapperPass
Legacy analysis pass which computes a MachineCycleInfo.
Definition: MachineCycleAnalysis.h:31
Machine
COFF::MachineTypes Machine
Definition: COFFYAML.cpp:370
llvm::initializeMachineCycleInfoPrinterPassPass
void initializeMachineCycleInfoPrinterPassPass(PassRegistry &)
GenericCycleImpl.h
true
machine Machine Cycle Info true
Definition: MachineCycleAnalysis.cpp:30
llvm::GenericCycle::contains
bool contains(const BlockT *Block) const
Return whether Block is contained in the cycle.
Definition: GenericCycleInfo.h:111
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(MachineCycleInfoWrapperPass, "machine-cycles", "Machine Cycle Info Analysis", true, true) INITIALIZE_PASS_END(MachineCycleInfoWrapperPass