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16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
46 X86::FeatureLAHFSAHF64,
49 X86::FeatureSSEUnalignedMem,
52 X86::TuningFast11ByteNOP,
53 X86::TuningFast15ByteNOP,
55 X86::TuningFastHorizontalOps,
57 X86::TuningFastScalarFSQRT,
58 X86::TuningFastSHLDRotate,
59 X86::TuningFastScalarShiftMasks,
60 X86::TuningFastVectorShiftMasks,
61 X86::TuningFastVariableCrossLaneShuffle,
62 X86::TuningFastVariablePerLaneShuffle,
63 X86::TuningFastVectorFSQRT,
66 X86::TuningLZCNTFalseDeps,
67 X86::TuningBranchFusion,
68 X86::TuningMacroFusion,
69 X86::TuningPadShortFunctions,
70 X86::TuningPOPCNTFalseDeps,
71 X86::TuningMULCFalseDeps,
72 X86::TuningPERMFalseDeps,
73 X86::TuningRANGEFalseDeps,
74 X86::TuningGETMANTFalseDeps,
75 X86::TuningMULLQFalseDeps,
76 X86::TuningSlow3OpsLEA,
77 X86::TuningSlowDivide32,
78 X86::TuningSlowDivide64,
79 X86::TuningSlowIncDec,
81 X86::TuningSlowPMADDWD,
82 X86::TuningSlowPMULLD,
84 X86::TuningSlowTwoMemOps,
85 X86::TuningSlowUAMem16,
86 X86::TuningPreferMaskRegisters,
87 X86::TuningInsertVZEROUPPER,
88 X86::TuningUseSLMArithCosts,
89 X86::TuningUseGLMDivSqrtCosts,
92 X86::TuningFastGather,
93 X86::TuningSlowUAMem32,
96 X86::TuningPrefer128Bit,
97 X86::TuningPrefer256Bit,
106 TLI(ST->getTargetLowering()) {}
152 const APInt &DemandedElts,
153 bool Insert,
bool Extract);
156 const APInt &DemandedDstElts,
166 const Value *Ptr,
bool VariableMask,
178 bool &KnownBitsComputed)
const;
183 SimplifyAndSetOp)
const;
206 bool UseMaskForCond =
false,
bool UseMaskForGaps =
false);
211 bool UseMaskForGaps =
false);
253 bool IsZeroCmp)
const;
259 bool supportsGather()
const;
261 bool VariableMask,
Align Alignment,
267 int getGatherOverhead()
const;
268 int getScatterOverhead()
const;
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind)
Optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, const TargetTransformInfo::LSRCost &C2)
InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, bool IsUnsigned, TTI::TargetCostKind CostKind)
This is an optimization pass for GlobalISel generic memory operations.
bool isLegalMaskedCompressStore(Type *DataType)
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth)
instcombine should handle this C2 when C1
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
bool isLegalMaskedGather(Type *DataType, Align Alignment)
The main scalar evolution driver.
bool isLegalMaskedExpandLoad(Type *DataType)
The instances of the Type class are immutable: once they are created, they are never changed.
Container class for subtarget features.
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef< int > Mask, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=None)
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I)
Calculate the cost of Gather / Scatter operation.
unsigned getLoadStoreVecRegBitWidth(unsigned AS) const
Class to represent fixed width SIMD vectors.
bool isLegalMaskedLoad(Type *DataType, Align Alignment)
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
bool isLegalNTLoad(Type *DataType, Align Alignment)
bool hasDivRemOp(Type *DataType, bool IsSigned)
Optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
bool isLegalMaskedStore(Type *DataType, Align Alignment)
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
This struct is a compact representation of a valid (non-zero power of two) alignment.
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, Optional< FastMathFlags > FMF, TTI::TargetCostKind CostKind)
Base class of all SIMD vector types.
unsigned getMaxInterleaveFactor(unsigned VF)
This class represents an analyzed expression in the program.
bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment)
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind)
InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, const SCEV *Ptr)
X86TTIImpl(const X86TargetMachine *TM, const Function &F)
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool isFCmpOrdCheaperThanFCmpZero(Type *Ty)
Base class which can be used to help build a TTI implementation.
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
bool supportsEfficientVectorElementLoadStore() const
bool isLegalNTStore(Type *DataType, Align Alignment)
InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned)
print Print MemDeps of function
Optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
Class for arbitrary precision integers.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
InstructionCost getIntImmCost(int64_t)
Calculate the cost of materializing a 64-bit value.
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
static const Function * getParent(const Value *V)
llvm::Optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const override
unsigned getAtomicMemIntrinsicMaxElementSize() const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index)
The core instruction combiner logic.
A wrapper class for inspecting calls to intrinsic functions.
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr)
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Type) const
InstructionCost getInterleavedMemoryOpCostAVX512(unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool isLegalMaskedScatter(Type *DataType, Align Alignment)
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I=nullptr)
InstructionCost getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond=false, bool UseMaskForGaps=false)
bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment)
InstructionCost getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
const char LLVMTargetMachineRef TM
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind)
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
llvm::Optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const override
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueKind Opd1Info=TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info=TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo=TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo=TTI::OP_None, ArrayRef< const Value * > Args=ArrayRef< const Value * >(), const Instruction *CxtI=nullptr)
LLVM Value Representation.
bool enableInterleavedAccessVectorization()
bool prefersVectorizedAddressing() const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract)
InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)