31#define DEBUG_TYPE "M68k-expand-pseudos"
56 MachineFunctionProperties::Property::NoVRegs);
60 return "M68k pseudo instruction expansion pass";
67char M68kExpandPseudo::ID = 0;
77 unsigned Opcode =
MI.getOpcode();
88 case M68k::MOVXd32d16:
91 case M68k::MOVSXd16d8:
93 case M68k::MOVSXd32d8:
95 case M68k::MOVSXd32d16:
98 case M68k::MOVZXd16d8:
100 case M68k::MOVZXd32d8:
102 case M68k::MOVZXd32d16:
105 case M68k::MOVSXd16j8:
106 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj),
MVT::i16,
108 case M68k::MOVSXd32j8:
109 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj),
MVT::i32,
111 case M68k::MOVSXd32j16:
112 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rj),
MVT::i32,
115 case M68k::MOVZXd16j8:
116 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj),
MVT::i16,
118 case M68k::MOVZXd32j8:
119 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj),
MVT::i32,
121 case M68k::MOVZXd32j16:
122 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rj),
MVT::i32,
125 case M68k::MOVSXd16p8:
126 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp),
MVT::i16,
128 case M68k::MOVSXd32p8:
129 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp),
MVT::i32,
131 case M68k::MOVSXd32p16:
132 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rp),
MVT::i32,
135 case M68k::MOVZXd16p8:
136 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp),
MVT::i16,
138 case M68k::MOVZXd32p8:
139 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp),
MVT::i32,
141 case M68k::MOVZXd32p16:
142 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rp),
MVT::i32,
145 case M68k::MOVSXd16f8:
146 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df),
MVT::i16,
148 case M68k::MOVSXd32f8:
149 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df),
MVT::i32,
151 case M68k::MOVSXd32f16:
152 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rf),
MVT::i32,
155 case M68k::MOVZXd16f8:
156 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df),
MVT::i16,
158 case M68k::MOVZXd32f8:
159 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df),
MVT::i32,
161 case M68k::MOVZXd32f16:
162 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rf),
MVT::i32,
166 return TII->ExpandCCR(MIB,
true);
168 return TII->ExpandCCR(MIB,
false);
170 case M68k::MOVM8jm_P:
171 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
172 case M68k::MOVM16jm_P:
173 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
174 case M68k::MOVM32jm_P:
175 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
177 case M68k::MOVM8pm_P:
178 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
179 case M68k::MOVM16pm_P:
180 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
181 case M68k::MOVM32pm_P:
182 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
184 case M68k::MOVM8mj_P:
185 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
186 case M68k::MOVM16mj_P:
187 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
188 case M68k::MOVM32mj_P:
189 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
191 case M68k::MOVM8mp_P:
192 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
193 case M68k::MOVM16mp_P:
194 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
195 case M68k::MOVM32mp_P:
196 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
198 case M68k::TCRETURNq:
199 case M68k::TCRETURNj: {
202 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
205 int StackAdj = StackAdjust.
getImm();
206 int MaxTCDelta = MFI->getTCReturnAddrDelta();
208 assert(MaxTCDelta <= 0 &&
"MaxTCDelta should never be positive");
211 Offset = StackAdj - MaxTCDelta;
212 assert(
Offset >= 0 &&
"Offset should never be negative");
221 if (Opcode == M68k::TCRETURNq) {
247 int64_t StackAdj =
MBBI->getOperand(0).getImm();
252 }
else if (isUInt<16>(StackAdj)) {
254 if (STI->atLeastM68020()) {
263 FL->emitSPUpdate(
MBB,
MBBI, StackAdj,
true);
306 TII = STI->getInstrInfo();
307 TRI = STI->getRegisterInfo();
309 FL = STI->getFrameLowering();
319 return new M68kExpandPseudo();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
const HexagonInstrInfo * TII
This file contains the M68k declaration of TargetFrameLowering class.
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the M68k specific subclass of MachineFunctionInfo.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file contains the entry points for global functions defined in the M68k target library,...
unsigned const TargetRegisterInfo * TRI
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
int64_t getOffset() const
Return the offset from the symbol in this operand.
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
StringRef - Represent a constant reference to a string, i.e.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
FunctionPass * createM68kExpandPseudoPass()
Return a Machine IR pass that expands M68k-specific pseudo instructions into a sequence of actual ins...