31#define DEBUG_TYPE "m68k-expand-pseudo"
32#define PASS_NAME "M68k pseudo instruction expansion pass"
57 MachineFunctionProperties::Property::NoVRegs);
64char M68kExpandPseudo::ID = 0;
76 unsigned Opcode =
MI.getOpcode();
84 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
86 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
87 case M68k::MOVXd32d16:
88 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
90 case M68k::MOVSXd16d8:
91 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i16, MVT::i8);
92 case M68k::MOVSXd32d8:
93 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i32, MVT::i8);
94 case M68k::MOVSXd32d16:
95 return TII->ExpandMOVSZX_RR(MIB,
true, MVT::i32, MVT::i16);
97 case M68k::MOVZXd16d8:
98 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i16, MVT::i8);
99 case M68k::MOVZXd32d8:
100 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i32, MVT::i8);
101 case M68k::MOVZXd32d16:
102 return TII->ExpandMOVSZX_RR(MIB,
false, MVT::i32, MVT::i16);
104 case M68k::MOVSXd16j8:
105 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj), MVT::i16,
107 case M68k::MOVSXd32j8:
108 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dj), MVT::i32,
110 case M68k::MOVSXd32j16:
111 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rj), MVT::i32,
114 case M68k::MOVZXd16j8:
115 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj), MVT::i16,
117 case M68k::MOVZXd32j8:
118 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dj), MVT::i32,
120 case M68k::MOVZXd32j16:
121 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rj), MVT::i32,
124 case M68k::MOVSXd16p8:
125 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp), MVT::i16,
127 case M68k::MOVSXd32p8:
128 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dp), MVT::i32,
130 case M68k::MOVSXd32p16:
131 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rp), MVT::i32,
134 case M68k::MOVZXd16p8:
135 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp), MVT::i16,
137 case M68k::MOVZXd32p8:
138 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dp), MVT::i32,
140 case M68k::MOVZXd32p16:
141 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rp), MVT::i32,
144 case M68k::MOVSXd16f8:
145 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df), MVT::i16,
147 case M68k::MOVSXd32f8:
148 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8df), MVT::i32,
150 case M68k::MOVSXd32f16:
151 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16rf), MVT::i32,
154 case M68k::MOVZXd16f8:
155 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df), MVT::i16,
157 case M68k::MOVZXd32f8:
158 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8df), MVT::i32,
160 case M68k::MOVZXd32f16:
161 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16rf), MVT::i32,
164 case M68k::MOVSXd16q8:
165 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dq), MVT::i16,
167 case M68k::MOVSXd32q8:
168 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV8dq), MVT::i32,
170 case M68k::MOVSXd32q16:
171 return TII->ExpandMOVSZX_RM(MIB,
true,
TII->get(M68k::MOV16dq), MVT::i32,
174 case M68k::MOVZXd16q8:
175 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dq), MVT::i16,
177 case M68k::MOVZXd32q8:
178 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV8dq), MVT::i32,
180 case M68k::MOVZXd32q16:
181 return TII->ExpandMOVSZX_RM(MIB,
false,
TII->get(M68k::MOV16dq), MVT::i32,
185 return TII->ExpandCCR(MIB,
true);
187 return TII->ExpandCCR(MIB,
false);
189 case M68k::MOVM8jm_P:
190 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
191 case M68k::MOVM16jm_P:
192 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
193 case M68k::MOVM32jm_P:
194 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32jm),
false);
196 case M68k::MOVM8pm_P:
197 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
198 case M68k::MOVM16pm_P:
199 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
200 case M68k::MOVM32pm_P:
201 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32pm),
false);
203 case M68k::MOVM8mj_P:
204 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
205 case M68k::MOVM16mj_P:
206 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
207 case M68k::MOVM32mj_P:
208 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mj),
true);
210 case M68k::MOVM8mp_P:
211 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
212 case M68k::MOVM16mp_P:
213 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
214 case M68k::MOVM32mp_P:
215 return TII->ExpandMOVEM(MIB,
TII->get(M68k::MOVM32mp),
true);
217 case M68k::TCRETURNq:
218 case M68k::TCRETURNj: {
221 assert(StackAdjust.
isImm() &&
"Expecting immediate value.");
224 int StackAdj = StackAdjust.
getImm();
225 int MaxTCDelta = MFI->getTCReturnAddrDelta();
227 assert(MaxTCDelta <= 0 &&
"MaxTCDelta should never be positive");
230 Offset = StackAdj - MaxTCDelta;
231 assert(
Offset >= 0 &&
"Offset should never be negative");
240 if (Opcode == M68k::TCRETURNq) {
268 }
else if (int64_t StackAdj =
MBBI->getOperand(0).getImm(); StackAdj == 0) {
277 FL->emitSPUpdate(
MBB,
MBBI, StackAdj,
true);
314 TII = STI->getInstrInfo();
315 TRI = STI->getRegisterInfo();
317 FL = STI->getFrameLowering();
327 return new M68kExpandPseudo();
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
This file contains the M68k declaration of TargetFrameLowering class.
This file contains the M68k implementation of the TargetInstrInfo class.
This file declares the M68k specific subclass of MachineFunctionInfo.
This file declares the M68k specific subclass of TargetSubtargetInfo.
This file contains the entry points for global functions defined in the M68k target library,...
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Represent the analysis usage information of a pass.
AnalysisUsage & addPreservedID(const void *ID)
void setPreservesCFG()
This function should be called by the pass, iff they do not:
FunctionPass class - This class is used to implement most global optimizations.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Representation of each machine instruction.
void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
MachineOperand class - Representation of each machine instruction operand.
const GlobalValue * getGlobal() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
unsigned getTargetFlags() const
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
const char * getSymbolName() const
Register getReg() const
getReg - Returns the register number.
int64_t getOffset() const
Return the offset from the symbol in this operand.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ M68k_INTR
Used for M68k interrupt routines.
@ Kill
The last use of a register.
This is an optimization pass for GlobalISel generic memory operations.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
FunctionPass * createM68kExpandPseudoPass()
Return a Machine IR pass that expands M68k-specific pseudo instructions into a sequence of actual ins...