LLVM 24.0.0git
M68kExpandPseudo.cpp
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1//===-- M68kExpandPseudo.cpp - Expand pseudo instructions -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file contains a pass that expands pseudo instructions into target
11/// instructions to allow proper scheduling, if-conversion, other late
12/// optimizations, or simply the encoding of the instructions.
13///
14//===----------------------------------------------------------------------===//
15
16#include "M68k.h"
17#include "M68kFrameLowering.h"
18#include "M68kInstrInfo.h"
19#include "M68kMachineFunction.h"
20#include "M68kSubtarget.h"
21
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
26#include "llvm/IR/EHPersonalities.h"
27#include "llvm/IR/GlobalValue.h"
28
29using namespace llvm;
30
31#define DEBUG_TYPE "m68k-expand-pseudo"
32#define PASS_NAME "M68k pseudo instruction expansion pass"
33
34namespace {
35class M68kExpandPseudo : public MachineFunctionPass {
36public:
37 static char ID;
38 M68kExpandPseudo() : MachineFunctionPass(ID) {}
39
40 void getAnalysisUsage(AnalysisUsage &AU) const override {
41 AU.setPreservesCFG();
42 AU.addPreservedID(MachineLoopInfoID);
43 AU.addPreservedID(MachineDominatorsID);
44 MachineFunctionPass::getAnalysisUsage(AU);
45 }
46
47 const M68kSubtarget *STI;
48 const M68kInstrInfo *TII;
49 const M68kRegisterInfo *TRI;
50 const M68kMachineFunctionInfo *MFI;
51 const M68kFrameLowering *FL;
52
53 bool runOnMachineFunction(MachineFunction &Fn) override;
54
55 MachineFunctionProperties getRequiredProperties() const override {
56 return MachineFunctionProperties().setNoVRegs();
57 }
58
59private:
60 bool ExpandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
61 bool ExpandMBB(MachineBasicBlock &MBB);
62};
63char M68kExpandPseudo::ID = 0;
64} // End anonymous namespace.
65
66INITIALIZE_PASS(M68kExpandPseudo, DEBUG_TYPE, PASS_NAME, false, false)
67
68/// If \p MBBI is a pseudo instruction, this method expands
69/// it to the corresponding (sequence of) actual instruction(s).
70/// \returns true if \p MBBI has been expanded.
71bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
72 MachineBasicBlock::iterator MBBI) {
73 MachineInstr &MI = *MBBI;
74 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
75 unsigned Opcode = MI.getOpcode();
76 DebugLoc DL = MBBI->getDebugLoc();
77 /// TODO infer argument size to create less switch cases
78 switch (Opcode) {
79 default:
80 return false;
81
82 case M68k::MOVI8di:
83 return TII->ExpandMOVI(MIB, MVT::i8);
84 case M68k::MOVI16di:
85 return TII->ExpandMOVI(MIB, MVT::i16);
86 case M68k::MOVI32ri:
87 return TII->ExpandMOVI(MIB, MVT::i32);
88
89 case M68k::MOVSXd16d8:
90 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8);
91 case M68k::MOVSXd32d8:
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8);
93 case M68k::MOVSXr32r16:
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16);
95
96 case M68k::MOVZXd16d8:
97 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8);
98 case M68k::MOVZXd32d8:
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8);
100 case M68k::MOVZXd32r16:
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16);
102
103 case M68k::MOVXd16d8:
104 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8);
105 case M68k::MOVXd32d8:
106 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8);
107 case M68k::MOVXr32r16:
108 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16);
109
110 case M68k::MOVSXd16o8:
111 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8do, MVT::i16, MVT::i8);
112 case M68k::MOVSXd16e8:
113 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8de, MVT::i16, MVT::i8);
114 case M68k::MOVSXd16k8:
115 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dk, MVT::i16, MVT::i8);
116 case M68k::MOVSXd16q8:
117 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dq, MVT::i16, MVT::i8);
118 case M68k::MOVSXd16f8:
119 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8df, MVT::i16, MVT::i8);
120 case M68k::MOVSXd16p8:
121 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dp, MVT::i16, MVT::i8);
122 case M68k::MOVSXd16b8:
123 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8db, MVT::i16, MVT::i8);
124 case M68k::MOVSXd16j8:
125 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dj, MVT::i16, MVT::i8);
126
127 case M68k::MOVSXd32o8:
128 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8do, MVT::i32, MVT::i8);
129 case M68k::MOVSXd32e8:
130 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8de, MVT::i32, MVT::i8);
131 case M68k::MOVSXd32k8:
132 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dk, MVT::i32, MVT::i8);
133 case M68k::MOVSXd32q8:
134 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dq, MVT::i32, MVT::i8);
135 case M68k::MOVSXd32f8:
136 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8df, MVT::i32, MVT::i8);
137 case M68k::MOVSXd32p8:
138 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dp, MVT::i32, MVT::i8);
139 case M68k::MOVSXd32b8:
140 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8db, MVT::i32, MVT::i8);
141 case M68k::MOVSXd32j8:
142 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV8dj, MVT::i32, MVT::i8);
143
144 case M68k::MOVSXr32o16:
145 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16ro, MVT::i32, MVT::i16);
146 case M68k::MOVSXr32e16:
147 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16re, MVT::i32, MVT::i16);
148 case M68k::MOVSXr32k16:
149 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rk, MVT::i32, MVT::i16);
150 case M68k::MOVSXr32q16:
151 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rq, MVT::i32, MVT::i16);
152 case M68k::MOVSXr32f16:
153 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rf, MVT::i32, MVT::i16);
154 case M68k::MOVSXr32p16:
155 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rp, MVT::i32, MVT::i16);
156 case M68k::MOVSXr32b16:
157 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rb, MVT::i32, MVT::i16);
158 case M68k::MOVSXr32j16:
159 return TII->ExpandMOVSZX_RM(MIB, true, M68k::MOV16rj, MVT::i32, MVT::i16);
160
161 case M68k::MOVZXd16o8:
162 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8do, MVT::i16, MVT::i8);
163 case M68k::MOVZXd16e8:
164 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8de, MVT::i16, MVT::i8);
165 case M68k::MOVZXd16k8:
166 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dk, MVT::i16, MVT::i8);
167 case M68k::MOVZXd16q8:
168 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dq, MVT::i16, MVT::i8);
169 case M68k::MOVZXd16f8:
170 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8df, MVT::i16, MVT::i8);
171 case M68k::MOVZXd16p8:
172 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dp, MVT::i16, MVT::i8);
173 case M68k::MOVZXd16b8:
174 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8db, MVT::i16, MVT::i8);
175 case M68k::MOVZXd16j8:
176 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dj, MVT::i16, MVT::i8);
177
178 case M68k::MOVZXd32o8:
179 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8do, MVT::i32, MVT::i8);
180 case M68k::MOVZXd32e8:
181 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8de, MVT::i32, MVT::i8);
182 case M68k::MOVZXd32k8:
183 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dk, MVT::i32, MVT::i8);
184 case M68k::MOVZXd32q8:
185 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dq, MVT::i32, MVT::i8);
186 case M68k::MOVZXd32f8:
187 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8df, MVT::i32, MVT::i8);
188 case M68k::MOVZXd32p8:
189 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dp, MVT::i32, MVT::i8);
190 case M68k::MOVZXd32b8:
191 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8db, MVT::i32, MVT::i8);
192 case M68k::MOVZXd32j8:
193 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV8dj, MVT::i32, MVT::i8);
194
195 case M68k::MOVZXd32o16:
196 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16ro, MVT::i32, MVT::i16);
197 case M68k::MOVZXd32e16:
198 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16re, MVT::i32, MVT::i16);
199 case M68k::MOVZXd32k16:
200 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rk, MVT::i32, MVT::i16);
201 case M68k::MOVZXd32q16:
202 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rq, MVT::i32, MVT::i16);
203 case M68k::MOVZXd32f16:
204 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rf, MVT::i32, MVT::i16);
205 case M68k::MOVZXd32p16:
206 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rp, MVT::i32, MVT::i16);
207 case M68k::MOVZXd32b16:
208 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rb, MVT::i32, MVT::i16);
209 case M68k::MOVZXd32j16:
210 return TII->ExpandMOVSZX_RM(MIB, false, M68k::MOV16rj, MVT::i32, MVT::i16);
211
212 case M68k::MOVXd16o8:
213 return TII->ExpandMOVX_RM(MIB, M68k::MOV8do, MVT::i16, MVT::i8);
214 case M68k::MOVXd16e8:
215 return TII->ExpandMOVX_RM(MIB, M68k::MOV8de, MVT::i16, MVT::i8);
216 case M68k::MOVXd16k8:
217 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dk, MVT::i16, MVT::i8);
218 case M68k::MOVXd16q8:
219 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dq, MVT::i16, MVT::i8);
220 case M68k::MOVXd16f8:
221 return TII->ExpandMOVX_RM(MIB, M68k::MOV8df, MVT::i16, MVT::i8);
222 case M68k::MOVXd16p8:
223 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dp, MVT::i16, MVT::i8);
224 case M68k::MOVXd16b8:
225 return TII->ExpandMOVX_RM(MIB, M68k::MOV8db, MVT::i16, MVT::i8);
226 case M68k::MOVXd16j8:
227 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dj, MVT::i16, MVT::i8);
228
229 case M68k::MOVXd32o8:
230 return TII->ExpandMOVX_RM(MIB, M68k::MOV8do, MVT::i32, MVT::i8);
231 case M68k::MOVXd32e8:
232 return TII->ExpandMOVX_RM(MIB, M68k::MOV8de, MVT::i32, MVT::i8);
233 case M68k::MOVXd32k8:
234 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dk, MVT::i32, MVT::i8);
235 case M68k::MOVXd32q8:
236 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dq, MVT::i32, MVT::i8);
237 case M68k::MOVXd32f8:
238 return TII->ExpandMOVX_RM(MIB, M68k::MOV8df, MVT::i32, MVT::i8);
239 case M68k::MOVXd32p8:
240 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dp, MVT::i32, MVT::i8);
241 case M68k::MOVXd32b8:
242 return TII->ExpandMOVX_RM(MIB, M68k::MOV8db, MVT::i32, MVT::i8);
243 case M68k::MOVXd32j8:
244 return TII->ExpandMOVX_RM(MIB, M68k::MOV8dj, MVT::i32, MVT::i8);
245
246 case M68k::MOVXr32o16:
247 return TII->ExpandMOVX_RM(MIB, M68k::MOV16ro, MVT::i32, MVT::i16);
248 case M68k::MOVXr32e16:
249 return TII->ExpandMOVX_RM(MIB, M68k::MOV16re, MVT::i32, MVT::i16);
250 case M68k::MOVXr32k16:
251 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rk, MVT::i32, MVT::i16);
252 case M68k::MOVXr32q16:
253 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rq, MVT::i32, MVT::i16);
254 case M68k::MOVXr32f16:
255 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rf, MVT::i32, MVT::i16);
256 case M68k::MOVXr32p16:
257 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rp, MVT::i32, MVT::i16);
258 case M68k::MOVXr32b16:
259 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rb, MVT::i32, MVT::i16);
260 case M68k::MOVXr32j16:
261 return TII->ExpandMOVX_RM(MIB, M68k::MOV16rj, MVT::i32, MVT::i16);
262
263 case M68k::MOVM8jm_P:
264 case M68k::MOVM16jm_P:
265 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16jm), /*IsRM=*/false);
266 case M68k::MOVM32jm_P:
267 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32jm), /*IsRM=*/false);
268
269 case M68k::MOVM8pm_P:
270 case M68k::MOVM16pm_P:
271 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16pm), /*IsRM=*/false);
272 case M68k::MOVM32pm_P:
273 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32pm), /*IsRM=*/false);
274
275 case M68k::MOVM8mj_P:
276 case M68k::MOVM16mj_P:
277 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16mj), /*IsRM=*/true);
278 case M68k::MOVM32mj_P:
279 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mj), /*IsRM=*/true);
280
281 case M68k::MOVM8mp_P:
282 case M68k::MOVM16mp_P:
283 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM16mp), /*IsRM=*/true);
284 case M68k::MOVM32mp_P:
285 return TII->ExpandMOVEM(MIB, TII->get(M68k::MOVM32mp), /*IsRM=*/true);
286
287 case M68k::TCRETURNq:
288 case M68k::TCRETURNj: {
289 MachineOperand &JumpTarget = MI.getOperand(0);
290 MachineOperand &StackAdjust = MI.getOperand(1);
291 assert(StackAdjust.isImm() && "Expecting immediate value.");
292
293 // Adjust stack pointer.
294 int StackAdj = StackAdjust.getImm();
295 int MaxTCDelta = MFI->getTCReturnAddrDelta();
296 int Offset = 0;
297 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
298
299 // Incoporate the retaddr area.
300 Offset = StackAdj - MaxTCDelta;
301 assert(Offset >= 0 && "Offset should never be negative");
302
303 if (Offset) {
304 // Check for possible merge with preceding ADD instruction.
305 Offset += FL->mergeSPUpdates(MBB, MBBI, true);
306 FL->emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
307 }
308
309 // Jump to label or value in register.
310 if (Opcode == M68k::TCRETURNq) {
311 MachineInstrBuilder MIB =
312 BuildMI(MBB, MBBI, DL, TII->get(M68k::TAILJMPq));
313 if (JumpTarget.isGlobal()) {
314 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
315 JumpTarget.getTargetFlags());
316 } else {
317 assert(JumpTarget.isSymbol());
318 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
319 JumpTarget.getTargetFlags());
320 }
321 } else {
322 BuildMI(MBB, MBBI, DL, TII->get(M68k::TAILJMPj))
323 .addReg(JumpTarget.getReg(), RegState::Kill);
324 }
325
326 MachineInstr &NewMI = *std::prev(MBBI);
327 NewMI.copyImplicitOps(*MBBI->getParent()->getParent(), *MBBI);
328
329 // Delete the pseudo instruction TCRETURN.
330 MBB.erase(MBBI);
331
332 return true;
333 }
334 case M68k::RET: {
335 if (MBB.getParent()->getFunction().getCallingConv() ==
336 CallingConv::M68k_INTR) {
337 BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
338 } else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
339 BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
340 } else {
341 // Copy return address from stack to a free address(A0 or A1) register
342 // TODO check if pseudo expand uses free address register
343 BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32aj), M68k::A1)
344 .addReg(M68k::SP);
345
346 // Adjust SP
347 FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
348
349 // Put the return address on stack
350 BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32ja))
351 .addReg(M68k::SP)
352 .addReg(M68k::A1);
353
354 // RTS
355 BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
356 }
357
358 // FIXME: Can rest of the operands be ignored, if there is any?
359 MBB.erase(MBBI);
360 return true;
361 }
362 }
363 llvm_unreachable("Previous switch has a fallthrough?");
364}
365
366/// Expand all pseudo instructions contained in \p MBB.
367/// \returns true if any expansion occurred for \p MBB.
368bool M68kExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
369 bool Modified = false;
370
371 // MBBI may be invalidated by the expansion.
372 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
373 while (MBBI != E) {
374 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
375 Modified |= ExpandMI(MBB, MBBI);
376 MBBI = NMBBI;
377 }
378
379 return Modified;
380}
381
382bool M68kExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
383 STI = &MF.getSubtarget<M68kSubtarget>();
384 TII = STI->getInstrInfo();
385 TRI = STI->getRegisterInfo();
386 MFI = MF.getInfo<M68kMachineFunctionInfo>();
387 FL = STI->getFrameLowering();
388
389 bool Modified = false;
390 for (MachineBasicBlock &MBB : MF)
391 Modified |= ExpandMBB(MBB);
392 return Modified;
393}
394
395/// Returns an instance of the pseudo instruction expansion pass.
396FunctionPass *llvm::createM68kExpandPseudoPass() {
397 return new M68kExpandPseudo();
398}
assert
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
MBB
MachineBasicBlock & MBB
Definition ARMSLSHardening.cpp:71
DL
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Definition ARMSLSHardening.cpp:73
MBBI
MachineBasicBlock MachineBasicBlock::iterator MBBI
Definition ARMSLSHardening.cpp:72
E
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
DEBUG_TYPE
#define DEBUG_TYPE
Definition GenericCycleImpl.h:34
TII
const HexagonInstrInfo * TII
Definition HexagonCopyToCombine.cpp:118
MI
IRTranslator LLVM IR MI
Definition IRTranslator.cpp:858
M68kFrameLowering.h
This file contains the M68k declaration of TargetFrameLowering class.
M68kInstrInfo.h
This file contains the M68k implementation of the TargetInstrInfo class.
M68kMachineFunction.h
This file declares the M68k specific subclass of MachineFunctionInfo.
M68kSubtarget.h
This file declares the M68k specific subclass of TargetSubtargetInfo.
M68k.h
This file contains the entry points for global functions defined in the M68k target library,...
TRI
Register const TargetRegisterInfo * TRI
Definition MachineSink.cpp:2128
INITIALIZE_PASS
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition PassSupport.h:56
PASS_NAME
#define PASS_NAME
Definition TypePromotion.cpp:43
llvm::AnalysisUsage
Represent the analysis usage information of a pass.
Definition PassAnalysisSupport.h:48
llvm::AnalysisUsage::addPreservedID
AnalysisUsage & addPreservedID(const void *ID)
Definition PassAnalysisSupport.h:89
llvm::AnalysisUsage::setPreservesCFG
LLVM_ABI void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition Pass.cpp:278
llvm::DebugLoc
A debug info location.
Definition DebugLoc.h:126
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition Pass.h:314
llvm::M68kSubtarget::getInstrInfo
const M68kInstrInfo * getInstrInfo() const override
Definition M68kSubtarget.h:150
llvm::M68kSubtarget::getRegisterInfo
const M68kRegisterInfo * getRegisterInfo() const override
Definition M68kSubtarget.h:156
llvm::M68kSubtarget::getFrameLowering
const M68kFrameLowering * getFrameLowering() const override
Definition M68kSubtarget.h:152
llvm::MachineBasicBlock::iterator
MachineInstrBundleIterator< MachineInstr > iterator
Definition MachineBasicBlock.h:341
llvm::MachineFunctionPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Definition MachineFunctionPass.h:31
llvm::MachineFunctionPass::getAnalysisUsage
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition MachineFunctionPass.cpp:148
llvm::MachineFunctionProperties
Properties which a MachineFunction may have at a given point in time.
Definition MachineFunction.h:138
llvm::MachineFunction::getSubtarget
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
Definition MachineFunction.h:778
llvm::MachineFunction::getInfo
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Definition MachineFunction.h:882
llvm::MachineInstrBuilder::addExternalSymbol
const MachineInstrBuilder & addExternalSymbol(const char *FnName, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:286
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, RegState Flags={}, unsigned SubReg=0) const
Add a new virtual register operand.
Definition MachineInstrBuilder.h:199
llvm::MachineInstrBuilder::addGlobalAddress
const MachineInstrBuilder & addGlobalAddress(const GlobalValue *GV, int64_t Offset=0, unsigned TargetFlags=0) const
Definition MachineInstrBuilder.h:279
llvm::MachineInstr
Representation of each machine instruction.
Definition MachineInstr.h:74
llvm::MachineInstr::copyImplicitOps
LLVM_ABI void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI)
Copy implicit register operands from specified instruction to this instruction.
Definition MachineInstr.cpp:1731
llvm::MachineOperand
MachineOperand class - Representation of each machine instruction operand.
Definition MachineOperand.h:49
llvm::MachineOperand::getGlobal
const GlobalValue * getGlobal() const
Definition MachineOperand.h:589
llvm::MachineOperand::getImm
int64_t getImm() const
Definition MachineOperand.h:563
llvm::MachineOperand::isImm
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Definition MachineOperand.h:336
llvm::MachineOperand::isSymbol
bool isSymbol() const
isSymbol - Tests if this is a MO_ExternalSymbol operand.
Definition MachineOperand.h:354
llvm::MachineOperand::getTargetFlags
unsigned getTargetFlags() const
Definition MachineOperand.h:232
llvm::MachineOperand::isGlobal
bool isGlobal() const
isGlobal - Tests if this is a MO_GlobalAddress operand.
Definition MachineOperand.h:352
llvm::MachineOperand::getSymbolName
const char * getSymbolName() const
Definition MachineOperand.h:649
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition MachineOperand.h:375
llvm::MachineOperand::getOffset
int64_t getOffset() const
Return the offset from the symbol in this operand.
Definition MachineOperand.h:641
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition ErrorHandling.h:164
llvm::CallingConv::M68k_INTR
@ M68k_INTR
Used for M68k interrupt routines.
Definition CallingConv.h:235
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition DefaultTargetInfo.h:21
llvm::Offset
@ Offset
Definition DWP.cpp:577
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition MachineInstrBuilder.h:449
llvm::RegState::Kill
@ Kill
The last use of a register.
Definition MachineInstrBuilder.h:61
llvm::MachineDominatorsID
LLVM_ABI char & MachineDominatorsID
MachineDominators - This pass is a machine dominators analysis pass.
Definition MachineDominators.cpp:99
llvm::MachineLoopInfoID
LLVM_ABI char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition MachineLoopInfo.cpp:65
llvm::createM68kExpandPseudoPass
FunctionPass * createM68kExpandPseudoPass()
Return a Machine IR pass that expands M68k-specific pseudo instructions into a sequence of actual ins...
Definition M68kExpandPseudo.cpp:396
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