Go to the documentation of this file.
16 #define DEBUG_TYPE "mir-vregnamer-utils"
21 cl::desc(
"Use Stable Hashing for MIR VReg Renaming"));
28 for (
const auto &
E : VRM) {
37 VRegRenamer::getVRegRenameMap(
const std::vector<NamedVReg> &VRegs) {
41 auto GetUniqueVRegName = [&VRegNameCollisionMap](
const NamedVReg &
Reg) {
42 if (VRegNameCollisionMap.
find(
Reg.getName()) == VRegNameCollisionMap.
end())
43 VRegNameCollisionMap[
Reg.getName()] = 0;
44 const unsigned Counter = ++VRegNameCollisionMap[
Reg.getName()];
49 for (
const auto &VReg : VRegs) {
50 const unsigned Reg = VReg.getReg();
51 VRM[
Reg] = createVirtualRegisterWithLowerName(
Reg, GetUniqueVRegName(VReg));
56 std::string VRegRenamer::getInstructionOpcodeHash(
MachineInstr &
MI) {
64 assert(Hash &&
"Expected non-zero Hash");
69 auto GetHashableMO = [
this](
const MachineOperand &MO) ->
unsigned {
70 switch (MO.getType()) {
73 MO.getCImm()->getZExtValue());
76 MO.getType(), MO.getTargetFlags(),
77 MO.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
85 return MO.getOffset() | (MO.getTargetFlags() << 16);
123 for (
const auto *
Op :
MI.memoperands()) {
124 MIOperands.push_back((
unsigned)
Op->getSize());
125 MIOperands.push_back((
unsigned)
Op->getFlags());
126 MIOperands.push_back((
unsigned)
Op->getOffset());
127 MIOperands.push_back((
unsigned)
Op->getSuccessOrdering());
128 MIOperands.push_back((
unsigned)
Op->getAddrSpace());
129 MIOperands.push_back((
unsigned)
Op->getSyncScopeID());
130 MIOperands.push_back((
unsigned)
Op->getBaseAlign().value());
131 MIOperands.push_back((
unsigned)
Op->getFailureOrdering());
138 unsigned VRegRenamer::createVirtualRegister(
unsigned VReg) {
141 return createVirtualRegisterWithLowerName(VReg,
Name);
145 std::vector<NamedVReg> VRegs;
149 if (Candidate.mayStore() || Candidate.isBranch())
151 if (!Candidate.getNumOperands())
159 NamedVReg(MO.
getReg(),
Prefix + getInstructionOpcodeHash(Candidate)));
162 return VRegs.size() ? doVRegRenaming(getVRegRenameMap(VRegs)) :
false;
165 unsigned VRegRenamer::createVirtualRegisterWithLowerName(
unsigned VReg,
167 std::string LowerName =
Name.lower();
@ MO_BlockAddress
Address of a basic block.
@ MO_Immediate
Immediate operand.
This is an optimization pass for GlobalISel generic memory operations.
Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
@ MO_ShuffleMask
Other IR Constant for ISel (shuffle masks)
@ MO_RegisterLiveOut
Mask of live-out registers.
A raw_ostream that writes to an std::string.
Reg
All possible values of the reg field in the ModR/M byte.
@ MO_CFIIndex
MCCFIInstruction index.
iterator find(StringRef Key)
hash_code hash_value(const APFloat &Arg)
See friend declarations above.
@ MO_Register
Register operand.
@ MO_GlobalAddress
Address of a global value.
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
@ MO_FrameIndex
Abstract Stack Frame Index.
stable_hash stableHashValue(const MachineOperand &MO)
MachineOperand class - Representation of each machine instruction operand.
std::map< unsigned, unsigned > VRegRenameMap
MachineInstr * getVRegDef(Register Reg) const
getVRegDef - Return the machine instr that defines the specified virtual register or null if none is ...
@ MO_Metadata
Metadata reference (for debug info)
bool isReg() const
isReg - Tests if this is a MO_Register operand.
Representation of each machine instruction.
@ MO_Predicate
Generic predicate for ISel.
@ MO_MCSymbol
MCSymbol reference (for debug/eh info)
initializer< Ty > init(const Ty &Val)
static bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
const TargetRegisterClass * getRegClassOrNull(Register Reg) const
Return the register class of Reg, or null if Reg has not been assigned a register class yet.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_FPImmediate
Floating-point immediate operand.
Register createGenericVirtualRegister(LLT Ty, StringRef Name="")
Create and return a new generic virtual register with low-level type Ty.
Register getReg() const
getReg - Returns the register number.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_CImmediate
Immediate >64bit operand.
StringRef - Represent a constant reference to a string, i.e.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
add sub stmia L5 ldr r0 bl L_printf $stub Instead of a and a wouldn t it be better to do three moves *Return an aggregate type is even return S
@ MO_IntrinsicID
Intrinsic ID for ISel.
unsigned const MachineRegisterInfo * MRI
void replaceRegWith(Register FromReg, Register ToReg)
replaceRegWith - Replace all instances of FromReg with ToReg in the machine function.
@ MO_ExternalSymbol
Name of external global symbol.
bool reg_empty(Register RegNo) const
reg_empty - Return true if there are no instructions using or defining the specified register (it may...
LLT getType(Register Reg) const
Get the low-level type of Reg or LLT{} if Reg is not a generic (target independent) virtual register.
hash_code hash_combine(const Ts &...args)
Combine values into a single hash_code.
hash_code hash_combine_range(InputIteratorT first, InputIteratorT last)
Compute a hash_code for a sequence of values.
std::string to_string(const T &Value)
@ MO_RegisterMask
Mask of preserved registers.
static cl::opt< bool > UseStableNamerHash("mir-vreg-namer-use-stable-hash", cl::init(false), cl::Hidden, cl::desc("Use Stable Hashing for MIR VReg Renaming"))
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.