LLVM 17.0.0git
PPCExpandAtomicPseudoInsts.cpp
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1//===-- PPCExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands atomic pseudo instructions into
10// target instructions post RA. With such method, LL/SC loop is considered as
11// a whole blob and make spilling unlikely happens in the LL/SC loop.
12//
13//===----------------------------------------------------------------------===//
14
16#include "PPC.h"
17#include "PPCInstrInfo.h"
18#include "PPCTargetMachine.h"
19
23
24using namespace llvm;
25
26#define DEBUG_TYPE "ppc-atomic-expand"
27
28namespace {
29
30class PPCExpandAtomicPseudo : public MachineFunctionPass {
31public:
32 const PPCInstrInfo *TII;
33 const PPCRegisterInfo *TRI;
34 static char ID;
35
36 PPCExpandAtomicPseudo() : MachineFunctionPass(ID) {
38 }
39
40 bool runOnMachineFunction(MachineFunction &MF) override;
41
42private:
43 bool expandMI(MachineBasicBlock &MBB, MachineInstr &MI,
45 bool expandAtomicRMW128(MachineBasicBlock &MBB, MachineInstr &MI,
47 bool expandAtomicCmpSwap128(MachineBasicBlock &MBB, MachineInstr &MI,
49};
50
51static void PairedCopy(const PPCInstrInfo *TII, MachineBasicBlock &MBB,
53 Register Dest0, Register Dest1, Register Src0,
54 Register Src1) {
55 const MCInstrDesc &OR = TII->get(PPC::OR8);
56 const MCInstrDesc &XOR = TII->get(PPC::XOR8);
57 if (Dest0 == Src1 && Dest1 == Src0) {
58 // The most tricky case, swapping values.
59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1);
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1);
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1);
62 } else if (Dest0 != Src0 || Dest1 != Src1) {
63 if (Dest0 == Src1 || Dest1 != Src0) {
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1);
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0);
66 } else {
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0);
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1);
69 }
70 }
71}
72
73bool PPCExpandAtomicPseudo::runOnMachineFunction(MachineFunction &MF) {
74 bool Changed = false;
75 TII = static_cast<const PPCInstrInfo *>(MF.getSubtarget().getInstrInfo());
76 TRI = &TII->getRegisterInfo();
77 for (MachineBasicBlock &MBB : MF) {
79 MBBI != MBBE;) {
81 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
82 Changed |= expandMI(MBB, MI, NMBBI);
83 MBBI = NMBBI;
84 }
85 }
86 if (Changed)
87 MF.RenumberBlocks();
88 return Changed;
89}
90
91bool PPCExpandAtomicPseudo::expandMI(MachineBasicBlock &MBB, MachineInstr &MI,
93 switch (MI.getOpcode()) {
94 case PPC::ATOMIC_SWAP_I128:
95 case PPC::ATOMIC_LOAD_ADD_I128:
96 case PPC::ATOMIC_LOAD_SUB_I128:
97 case PPC::ATOMIC_LOAD_XOR_I128:
98 case PPC::ATOMIC_LOAD_NAND_I128:
99 case PPC::ATOMIC_LOAD_AND_I128:
100 case PPC::ATOMIC_LOAD_OR_I128:
101 return expandAtomicRMW128(MBB, MI, NMBBI);
102 case PPC::ATOMIC_CMP_SWAP_I128:
103 return expandAtomicCmpSwap128(MBB, MI, NMBBI);
104 case PPC::BUILD_QUADWORD: {
105 Register Dst = MI.getOperand(0).getReg();
106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0);
107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1);
108 Register Lo = MI.getOperand(1).getReg();
109 Register Hi = MI.getOperand(2).getReg();
110 PairedCopy(TII, MBB, MI, MI.getDebugLoc(), DstHi, DstLo, Hi, Lo);
111 MI.eraseFromParent();
112 return true;
113 }
114 default:
115 return false;
116 }
117}
118
119bool PPCExpandAtomicPseudo::expandAtomicRMW128(
122 const MCInstrDesc &LL = TII->get(PPC::LQARX);
123 const MCInstrDesc &SC = TII->get(PPC::STQCX);
124 DebugLoc DL = MI.getDebugLoc();
126 const BasicBlock *BB = MBB.getBasicBlock();
127 // Create layout of control flow.
131 MF->insert(MFI, LoopMBB);
132 MF->insert(MFI, ExitMBB);
133 ExitMBB->splice(ExitMBB->begin(), &MBB, std::next(MI.getIterator()),
134 MBB.end());
136 MBB.addSuccessor(LoopMBB);
137
138 // For non-min/max operations, control flow is kinda like:
139 // MBB:
140 // ...
141 // LoopMBB:
142 // lqarx in, ptr
143 // addc out.sub_x1, in.sub_x1, op.sub_x1
144 // adde out.sub_x0, in.sub_x0, op.sub_x0
145 // stqcx out, ptr
146 // bne- LoopMBB
147 // ExitMBB:
148 // ...
149 Register Old = MI.getOperand(0).getReg();
150 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0);
151 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1);
152 Register Scratch = MI.getOperand(1).getReg();
153 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0);
154 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1);
155 Register RA = MI.getOperand(2).getReg();
156 Register RB = MI.getOperand(3).getReg();
157 Register IncrLo = MI.getOperand(4).getReg();
158 Register IncrHi = MI.getOperand(5).getReg();
159 unsigned RMWOpcode = MI.getOpcode();
160
161 MachineBasicBlock *CurrentMBB = LoopMBB;
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB);
163
164 switch (RMWOpcode) {
165 case PPC::ATOMIC_SWAP_I128:
166 PairedCopy(TII, *CurrentMBB, CurrentMBB->end(), DL, ScratchHi, ScratchLo,
167 IncrHi, IncrLo);
168 break;
169 case PPC::ATOMIC_LOAD_ADD_I128:
170 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDC8), ScratchLo)
171 .addReg(IncrLo)
172 .addReg(OldLo);
173 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDE8), ScratchHi)
174 .addReg(IncrHi)
175 .addReg(OldHi);
176 break;
177 case PPC::ATOMIC_LOAD_SUB_I128:
178 BuildMI(CurrentMBB, DL, TII->get(PPC::SUBFC8), ScratchLo)
179 .addReg(IncrLo)
180 .addReg(OldLo);
181 BuildMI(CurrentMBB, DL, TII->get(PPC::SUBFE8), ScratchHi)
182 .addReg(IncrHi)
183 .addReg(OldHi);
184 break;
185
186#define TRIVIAL_ATOMICRMW(Opcode, Instr) \
187 case Opcode: \
188 BuildMI(CurrentMBB, DL, TII->get((Instr)), ScratchLo) \
189 .addReg(IncrLo) \
190 .addReg(OldLo); \
191 BuildMI(CurrentMBB, DL, TII->get((Instr)), ScratchHi) \
192 .addReg(IncrHi) \
193 .addReg(OldHi); \
194 break
195
196 TRIVIAL_ATOMICRMW(PPC::ATOMIC_LOAD_OR_I128, PPC::OR8);
197 TRIVIAL_ATOMICRMW(PPC::ATOMIC_LOAD_XOR_I128, PPC::XOR8);
198 TRIVIAL_ATOMICRMW(PPC::ATOMIC_LOAD_AND_I128, PPC::AND8);
199 TRIVIAL_ATOMICRMW(PPC::ATOMIC_LOAD_NAND_I128, PPC::NAND8);
200#undef TRIVIAL_ATOMICRMW
201 default:
202 llvm_unreachable("Unhandled atomic RMW operation");
203 }
204 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB);
205 BuildMI(CurrentMBB, DL, TII->get(PPC::BCC))
207 .addReg(PPC::CR0)
208 .addMBB(LoopMBB);
209 CurrentMBB->addSuccessor(LoopMBB);
210 CurrentMBB->addSuccessor(ExitMBB);
211 recomputeLiveIns(*LoopMBB);
212 recomputeLiveIns(*ExitMBB);
213 NMBBI = MBB.end();
214 MI.eraseFromParent();
215 return true;
216}
217
218bool PPCExpandAtomicPseudo::expandAtomicCmpSwap128(
221 const MCInstrDesc &LL = TII->get(PPC::LQARX);
222 const MCInstrDesc &SC = TII->get(PPC::STQCX);
223 DebugLoc DL = MI.getDebugLoc();
225 const BasicBlock *BB = MBB.getBasicBlock();
226 Register Old = MI.getOperand(0).getReg();
227 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0);
228 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1);
229 Register Scratch = MI.getOperand(1).getReg();
230 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0);
231 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1);
232 Register RA = MI.getOperand(2).getReg();
233 Register RB = MI.getOperand(3).getReg();
234 Register CmpLo = MI.getOperand(4).getReg();
235 Register CmpHi = MI.getOperand(5).getReg();
236 Register NewLo = MI.getOperand(6).getReg();
237 Register NewHi = MI.getOperand(7).getReg();
238 // Create layout of control flow.
239 // loop:
240 // old = lqarx ptr
241 // <compare old, cmp>
242 // bne 0, fail
243 // succ:
244 // stqcx new ptr
245 // bne 0, loop
246 // b exit
247 // fail:
248 // stqcx old ptr
249 // exit:
250 // ....
252 MachineBasicBlock *LoopCmpMBB = MF->CreateMachineBasicBlock(BB);
253 MachineBasicBlock *CmpSuccMBB = MF->CreateMachineBasicBlock(BB);
254 MachineBasicBlock *CmpFailMBB = MF->CreateMachineBasicBlock(BB);
256 MF->insert(MFI, LoopCmpMBB);
257 MF->insert(MFI, CmpSuccMBB);
258 MF->insert(MFI, CmpFailMBB);
259 MF->insert(MFI, ExitMBB);
260 ExitMBB->splice(ExitMBB->begin(), &MBB, std::next(MI.getIterator()),
261 MBB.end());
263 MBB.addSuccessor(LoopCmpMBB);
264 // Build loop.
265 MachineBasicBlock *CurrentMBB = LoopCmpMBB;
266 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB);
267 BuildMI(CurrentMBB, DL, TII->get(PPC::XOR8), ScratchLo)
268 .addReg(OldLo)
269 .addReg(CmpLo);
270 BuildMI(CurrentMBB, DL, TII->get(PPC::XOR8), ScratchHi)
271 .addReg(OldHi)
272 .addReg(CmpHi);
273 BuildMI(CurrentMBB, DL, TII->get(PPC::OR8_rec), ScratchLo)
274 .addReg(ScratchLo)
275 .addReg(ScratchHi);
276 BuildMI(CurrentMBB, DL, TII->get(PPC::BCC))
278 .addReg(PPC::CR0)
279 .addMBB(CmpFailMBB);
280 CurrentMBB->addSuccessor(CmpSuccMBB);
281 CurrentMBB->addSuccessor(CmpFailMBB);
282 // Build succ.
283 CurrentMBB = CmpSuccMBB;
284 PairedCopy(TII, *CurrentMBB, CurrentMBB->end(), DL, ScratchHi, ScratchLo,
285 NewHi, NewLo);
286 BuildMI(CurrentMBB, DL, SC).addReg(Scratch).addReg(RA).addReg(RB);
287 BuildMI(CurrentMBB, DL, TII->get(PPC::BCC))
289 .addReg(PPC::CR0)
290 .addMBB(LoopCmpMBB);
291 BuildMI(CurrentMBB, DL, TII->get(PPC::B)).addMBB(ExitMBB);
292 CurrentMBB->addSuccessor(LoopCmpMBB);
293 CurrentMBB->addSuccessor(ExitMBB);
294 CurrentMBB = CmpFailMBB;
295 BuildMI(CurrentMBB, DL, SC).addReg(Old).addReg(RA).addReg(RB);
296 CurrentMBB->addSuccessor(ExitMBB);
297
298 recomputeLiveIns(*LoopCmpMBB);
299 recomputeLiveIns(*CmpSuccMBB);
300 recomputeLiveIns(*CmpFailMBB);
301 recomputeLiveIns(*ExitMBB);
302 NMBBI = MBB.end();
303 MI.eraseFromParent();
304 return true;
305}
306
307} // namespace
308
309INITIALIZE_PASS(PPCExpandAtomicPseudo, DEBUG_TYPE, "PowerPC Expand Atomic",
310 false, false)
311
312char PPCExpandAtomicPseudo::ID = 0;
314 return new PPCExpandAtomicPseudo();
315}
MachineBasicBlock & MBB
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned const TargetRegisterInfo * TRI
#define TRIVIAL_ATOMICRMW(Opcode, Instr)
#define DEBUG_TYPE
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
SI optimize exec mask operations pre RA
LLVM Basic Block Representation.
Definition: BasicBlock.h:56
A debug info location.
Definition: DebugLoc.h:33
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *FromMBB)
Transfers all the successors, as in transferSuccessors, and update PHI operands in the successor bloc...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *bb=nullptr)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void RenumberBlocks(MachineBasicBlock *MBBFrom=nullptr)
RenumberBlocks - This discards all of the MachineBasicBlock numbers and recomputes them.
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
Representation of each machine instruction.
Definition: MachineInstr.h:68
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
virtual const TargetInstrInfo * getInstrInfo() const
self_iterator getIterator()
Definition: ilist_node.h:82
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
static void recomputeLiveIns(MachineBasicBlock &MBB)
Convenience function for recomputing live-in's for MBB.
Definition: LivePhysRegs.h:198
FunctionPass * createPPCExpandAtomicPseudoPass()
void initializePPCExpandAtomicPseudoPass(PassRegistry &)