LLVM 20.0.0git
SIFixVGPRCopies.cpp
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1//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Add implicit use of exec to vector register copies.
11///
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "GCNSubtarget.h"
18
19using namespace llvm;
20
21#define DEBUG_TYPE "si-fix-vgpr-copies"
22
23namespace {
24
25class SIFixVGPRCopies : public MachineFunctionPass {
26public:
27 static char ID;
28
29public:
30 SIFixVGPRCopies() : MachineFunctionPass(ID) {
32 }
33
34 void getAnalysisUsage(AnalysisUsage &AU) const override {
35 AU.setPreservesAll();
37 }
38
39 bool runOnMachineFunction(MachineFunction &MF) override;
40
41 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
42};
43
44} // End anonymous namespace.
45
46INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
47
48char SIFixVGPRCopies::ID = 0;
49
50char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
51
52bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
53 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
54 const SIRegisterInfo *TRI = ST.getRegisterInfo();
55 const SIInstrInfo *TII = ST.getInstrInfo();
56 bool Changed = false;
57
58 for (MachineBasicBlock &MBB : MF) {
59 for (MachineInstr &MI : MBB) {
60 switch (MI.getOpcode()) {
61 case AMDGPU::COPY:
62 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
63 MI.addOperand(MF,
64 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
65 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
66 Changed = true;
67 }
68 break;
69 default:
70 break;
71 }
72 }
73 }
74
75 return Changed;
76}
Provides AMDGPU specific target descriptions.
MachineBasicBlock & MBB
#define LLVM_DEBUG(...)
Definition: Debug.h:106
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:38
#define DEBUG_TYPE
Represent the analysis usage information of a pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Representation of each machine instruction.
Definition: MachineInstr.h:69
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:51
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeSIFixVGPRCopiesPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
char & SIFixVGPRCopiesID