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47 Ret +=
"-f128:64-n32";
73 bool Is64Bit,
bool JIT) {
109 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
110 Attribute FSAttr =
F.getFnAttribute(
"target-features");
120 bool softFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
123 FS +=
FS.empty() ?
"+soft-float" :
",+soft-float";
125 auto &
I = SubtargetMap[CPU +
FS];
145 return getTM<SparcTargetMachine>();
148 void addIRPasses()
override;
149 bool addInstSelector()
override;
150 void addPreEmitPass()
override;
155 return new SparcPassConfig(*
this, PM);
158 void SparcPassConfig::addIRPasses() {
164 bool SparcPassConfig::addInstSelector() {
169 void SparcPassConfig::addPreEmitPass(){
172 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
176 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
179 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
185 void SparcV8TargetMachine::anchor() { }
195 void SparcV9TargetMachine::anchor() { }
205 void SparcelTargetMachine::anchor() {}
This is an optimization pass for GlobalISel generic memory operations.
bool isValid() const
Return true if the attribute is any kind of attribute.
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
static bool is64Bit(const char *name)
Target - Wrapper for Target specific information.
Target & getTheSparcTarget()
Triple - Helper class for working with autoconf configuration names.
static CodeModel::Model getEffectiveSparcCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool Is64Bit, bool JIT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget()
FunctionPass * createSparcISelDag(SparcTargetMachine &TM)
createSparcISelDag - This pass converts a legalized DAG into a SPARC-specific DAG,...
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
Target & getTheSparcelTarget()
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
RegisterTargetMachine - Helper template for registering a target machine implementation,...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
FunctionPass * createSparcDelaySlotFillerPass()
createSparcDelaySlotFillerPass - Returns a pass that fills in delay slots in Sparc MachineFunctions
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
StringRef getValueAsString() const
Return the attribute's value as a string.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
#define LLVM_EXTERNAL_VISIBILITY
~SparcTargetMachine() override
static std::string computeDataLayout(const Triple &T, bool is64Bit)
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
const SparcSubtarget * getSubtargetImpl() const
StringRef - Represent a constant reference to a string, i.e.
Analysis the ScalarEvolution expression for r is this
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
Create an ILP32 architecture model.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class describes a target machine that is implemented with the LLVM target-independent code gener...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
const char LLVMTargetMachineRef TM
Target & getTheSparcV9Target()