LLVM  14.0.0git
SparcTargetMachine.cpp
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1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "SparcTargetMachine.h"
13 #include "LeonPasses.h"
14 #include "Sparc.h"
15 #include "SparcTargetObjectFile.h"
17 #include "llvm/CodeGen/Passes.h"
21 using namespace llvm;
22 
24  // Register the target.
28 }
29 
30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
31  // Sparc is typically big endian, but some are little.
32  std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
33  Ret += "-m:e";
34 
35  // Some ABIs have 32bit pointers.
36  if (!is64Bit)
37  Ret += "-p:32:32";
38 
39  // Alignments for 64 bit integers.
40  Ret += "-i64:64";
41 
42  // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
43  // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
44  if (is64Bit)
45  Ret += "-n32:64";
46  else
47  Ret += "-f128:64-n32";
48 
49  if (is64Bit)
50  Ret += "-S128";
51  else
52  Ret += "-S64";
53 
54  return Ret;
55 }
56 
58  return RM.getValueOr(Reloc::Static);
59 }
60 
61 // Code models. Some only make sense for 64-bit code.
62 //
63 // SunCC Reloc CodeModel Constraints
64 // abs32 Static Small text+data+bss linked below 2^32 bytes
65 // abs44 Static Medium text+data+bss linked below 2^44 bytes
66 // abs64 Static Large text smaller than 2^31 bytes
67 // pic13 PIC_ Small GOT < 2^13 bytes
68 // pic32 PIC_ Medium GOT < 2^32 bytes
69 //
70 // All code models require that the text segment is smaller than 2GB.
71 static CodeModel::Model
73  bool Is64Bit, bool JIT) {
74  if (CM) {
75  if (*CM == CodeModel::Tiny)
76  report_fatal_error("Target does not support the tiny CodeModel", false);
77  if (*CM == CodeModel::Kernel)
78  report_fatal_error("Target does not support the kernel CodeModel", false);
79  return *CM;
80  }
81  if (Is64Bit) {
82  if (JIT)
83  return CodeModel::Large;
85  }
86  return CodeModel::Small;
87 }
88 
89 /// Create an ILP32 architecture model
91  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
93  Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
94  : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
97  CM, getEffectiveRelocModel(RM), is64bit, JIT),
98  OL),
99  TLOF(std::make_unique<SparcELFTargetObjectFile>()),
100  Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit),
101  is64Bit(is64bit) {
102  initAsmInfo();
103 }
104 
106 
107 const SparcSubtarget *
109  Attribute CPUAttr = F.getFnAttribute("target-cpu");
110  Attribute FSAttr = F.getFnAttribute("target-features");
111 
112  std::string CPU =
113  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
114  std::string FS =
115  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
116 
117  // FIXME: This is related to the code below to reset the target options,
118  // we need to know whether or not the soft float flag is set on the
119  // function, so we can enable it as a subtarget feature.
120  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
121 
122  if (softFloat)
123  FS += FS.empty() ? "+soft-float" : ",+soft-float";
124 
125  auto &I = SubtargetMap[CPU + FS];
126  if (!I) {
127  // This needs to be done before we create a new subtarget since any
128  // creation will depend on the TM and the code generation flags on the
129  // function that reside in TargetOptions.
131  I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
132  this->is64Bit);
133  }
134  return I.get();
135 }
136 
137 namespace {
138 /// Sparc Code Generator Pass Configuration Options.
139 class SparcPassConfig : public TargetPassConfig {
140 public:
141  SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
142  : TargetPassConfig(TM, PM) {}
143 
144  SparcTargetMachine &getSparcTargetMachine() const {
145  return getTM<SparcTargetMachine>();
146  }
147 
148  void addIRPasses() override;
149  bool addInstSelector() override;
150  void addPreEmitPass() override;
151 };
152 } // namespace
153 
155  return new SparcPassConfig(*this, PM);
156 }
157 
158 void SparcPassConfig::addIRPasses() {
159  addPass(createAtomicExpandPass());
160 
162 }
163 
164 bool SparcPassConfig::addInstSelector() {
165  addPass(createSparcISelDag(getSparcTargetMachine()));
166  return false;
167 }
168 
169 void SparcPassConfig::addPreEmitPass(){
171 
172  if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
173  {
174  addPass(new InsertNOPLoad());
175  }
176  if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) {
177  addPass(new DetectRoundChange());
178  }
179  if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
180  {
181  addPass(new FixAllFDIVSQRT());
182  }
183 }
184 
185 void SparcV8TargetMachine::anchor() { }
186 
188  StringRef CPU, StringRef FS,
189  const TargetOptions &Options,
192  CodeGenOpt::Level OL, bool JIT)
193  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
194 
195 void SparcV9TargetMachine::anchor() { }
196 
198  StringRef CPU, StringRef FS,
199  const TargetOptions &Options,
202  CodeGenOpt::Level OL, bool JIT)
203  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
204 
205 void SparcelTargetMachine::anchor() {}
206 
208  StringRef CPU, StringRef FS,
209  const TargetOptions &Options,
212  CodeGenOpt::Level OL, bool JIT)
213  : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
SparcTargetInfo.h
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:167
llvm::TargetOptions
Definition: TargetOptions.h:124
llvm::SparcelTargetMachine::SparcelTargetMachine
SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SparcTargetMachine.cpp:207
llvm::Function
Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1023
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::getTheSparcTarget
Target & getTheSparcTarget()
Definition: SparcTargetInfo.cpp:13
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
getEffectiveSparcCodeModel
static CodeModel::Model getEffectiveSparcCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool Is64Bit, bool JIT)
Definition: SparcTargetMachine.cpp:72
LegacyPassManager.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
SparcTargetObjectFile.h
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
LLVMInitializeSparcTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget()
Definition: SparcTargetMachine.cpp:23
llvm::SparcELFTargetObjectFile
Definition: SparcTargetObjectFile.h:19
llvm::Triple::sparcel
@ sparcel
Definition: Triple.h:77
llvm::createSparcISelDag
FunctionPass * createSparcISelDag(SparcTargetMachine &TM)
createSparcISelDag - This pass converts a legalized DAG into a SPARC-specific DAG,...
Definition: SparcISelDAGToDAG.cpp:398
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
false
Definition: StackSlotColoring.cpp:142
llvm::getTheSparcelTarget
Target & getTheSparcelTarget()
Definition: SparcTargetInfo.cpp:21
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::DetectRoundChange
Definition: LeonPasses.h:54
llvm::createSparcDelaySlotFillerPass
FunctionPass * createSparcDelaySlotFillerPass()
createSparcDelaySlotFillerPass - Returns a pass that fills in delay slots in Sparc MachineFunctions
Definition: DelaySlotFiller.cpp:98
llvm::SparcV9TargetMachine::SparcV9TargetMachine
SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SparcTargetMachine.cpp:197
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:100
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
llvm::SparcSubtarget
Definition: SparcSubtarget.h:31
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::InsertNOPLoad
Definition: LeonPasses.h:40
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::SparcTargetMachine
Definition: SparcTargetMachine.h:22
llvm::FixAllFDIVSQRT
Definition: LeonPasses.h:68
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:98
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::SparcTargetMachine::~SparcTargetMachine
~SparcTargetMachine() override
Definition: SparcTargetMachine.cpp:105
computeDataLayout
static std::string computeDataLayout(const Triple &T, bool is64Bit)
Definition: SparcTargetMachine.cpp:30
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
llvm::SparcV8TargetMachine::SparcV8TargetMachine
SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SparcTargetMachine.cpp:187
TargetPassConfig.h
llvm::SparcTargetMachine::getSubtargetImpl
const SparcSubtarget * getSubtargetImpl() const
Definition: SparcTargetMachine.h:34
SparcTargetMachine.h
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::SparcTargetMachine::SparcTargetMachine
SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool is64bit)
Create an ILP32 architecture model.
Definition: SparcTargetMachine.cpp:90
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::SparcTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: SparcTargetMachine.cpp:154
std
Definition: BitVector.h:838
Sparc.h
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
LeonPasses.h
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1815
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:99
llvm::getTheSparcV9Target
Target & getTheSparcV9Target()
Definition: SparcTargetInfo.cpp:17
SpecialSubKind::string
@ string