LLVM  10.0.0svn
R600ExpandSpecialInstrs.cpp
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1 //===- R600ExpandSpecialInstrs.cpp - Expand special instructions ----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// Vector, Reduction, and Cube instructions need to fill the entire instruction
11 /// group to work correctly. This pass expands these individual instructions
12 /// into several instructions that will completely fill the instruction group.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "AMDGPU.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600Defines.h"
19 #include "R600InstrInfo.h"
20 #include "R600RegisterInfo.h"
28 #include "llvm/Pass.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <iterator>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "r600-expand-special-instrs"
36 
37 namespace {
38 
39 class R600ExpandSpecialInstrsPass : public MachineFunctionPass {
40 private:
41  const R600InstrInfo *TII = nullptr;
42 
43  void SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI,
44  unsigned Op);
45 
46 public:
47  static char ID;
48 
49  R600ExpandSpecialInstrsPass() : MachineFunctionPass(ID) {}
50 
51  bool runOnMachineFunction(MachineFunction &MF) override;
52 
53  StringRef getPassName() const override {
54  return "R600 Expand special instructions pass";
55  }
56 };
57 
58 } // end anonymous namespace
59 
60 INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
61  "R600 Expand Special Instrs", false, false)
62 INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass, DEBUG_TYPE,
64 
65 char R600ExpandSpecialInstrsPass::ID = 0;
66 
67 char &llvm::R600ExpandSpecialInstrsPassID = R600ExpandSpecialInstrsPass::ID;
68 
70  return new R600ExpandSpecialInstrsPass();
71 }
72 
73 void R600ExpandSpecialInstrsPass::SetFlagInNewMI(MachineInstr *NewMI,
74  const MachineInstr *OldMI, unsigned Op) {
75  int OpIdx = TII->getOperandIdx(*OldMI, Op);
76  if (OpIdx > -1) {
77  uint64_t Val = OldMI->getOperand(OpIdx).getImm();
78  TII->setImmOperand(*NewMI, Op, Val);
79  }
80 }
81 
82 bool R600ExpandSpecialInstrsPass::runOnMachineFunction(MachineFunction &MF) {
84  TII = ST.getInstrInfo();
85 
86  const R600RegisterInfo &TRI = TII->getRegisterInfo();
87 
88  for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
89  BB != BB_E; ++BB) {
90  MachineBasicBlock &MBB = *BB;
92  while (I != MBB.end()) {
93  MachineInstr &MI = *I;
94  I = std::next(I);
95 
96  // Expand LDS_*_RET instructions
97  if (TII->isLDSRetInstr(MI.getOpcode())) {
98  int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst);
99  assert(DstIdx != -1);
100  MachineOperand &DstOp = MI.getOperand(DstIdx);
101  MachineInstr *Mov = TII->buildMovInstr(&MBB, I,
102  DstOp.getReg(), R600::OQAP);
103  DstOp.setReg(R600::OQAP);
104  int LDSPredSelIdx = TII->getOperandIdx(MI.getOpcode(),
105  R600::OpName::pred_sel);
106  int MovPredSelIdx = TII->getOperandIdx(Mov->getOpcode(),
107  R600::OpName::pred_sel);
108  // Copy the pred_sel bit
109  Mov->getOperand(MovPredSelIdx).setReg(
110  MI.getOperand(LDSPredSelIdx).getReg());
111  }
112 
113  switch (MI.getOpcode()) {
114  default: break;
115  // Expand PRED_X to one of the PRED_SET instructions.
116  case R600::PRED_X: {
117  uint64_t Flags = MI.getOperand(3).getImm();
118  // The native opcode used by PRED_X is stored as an immediate in the
119  // third operand.
120  MachineInstr *PredSet = TII->buildDefaultInstruction(MBB, I,
121  MI.getOperand(2).getImm(), // opcode
122  MI.getOperand(0).getReg(), // dst
123  MI.getOperand(1).getReg(), // src0
124  R600::ZERO); // src1
125  TII->addFlag(*PredSet, 0, MO_FLAG_MASK);
126  if (Flags & MO_FLAG_PUSH) {
127  TII->setImmOperand(*PredSet, R600::OpName::update_exec_mask, 1);
128  } else {
129  TII->setImmOperand(*PredSet, R600::OpName::update_pred, 1);
130  }
131  MI.eraseFromParent();
132  continue;
133  }
134  case R600::DOT_4: {
135 
136  const R600RegisterInfo &TRI = TII->getRegisterInfo();
137 
138  Register DstReg = MI.getOperand(0).getReg();
139  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
140 
141  for (unsigned Chan = 0; Chan < 4; ++Chan) {
142  bool Mask = (Chan != TRI.getHWRegChan(DstReg));
143  unsigned SubDstReg =
144  R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
145  MachineInstr *BMI =
146  TII->buildSlotOfVectorInstruction(MBB, &MI, Chan, SubDstReg);
147  if (Chan > 0) {
148  BMI->bundleWithPred();
149  }
150  if (Mask) {
151  TII->addFlag(*BMI, 0, MO_FLAG_MASK);
152  }
153  if (Chan != 3)
154  TII->addFlag(*BMI, 0, MO_FLAG_NOT_LAST);
155  unsigned Opcode = BMI->getOpcode();
156  // While not strictly necessary from hw point of view, we force
157  // all src operands of a dot4 inst to belong to the same slot.
158  Register Src0 =
159  BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src0))
160  .getReg();
161  Register Src1 =
162  BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
163  .getReg();
164  (void) Src0;
165  (void) Src1;
166  if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
167  (TRI.getEncodingValue(Src1) & 0xff) < 127)
168  assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
169  }
170  MI.eraseFromParent();
171  continue;
172  }
173  }
174 
175  bool IsReduction = TII->isReductionOp(MI.getOpcode());
176  bool IsVector = TII->isVector(MI);
177  bool IsCube = TII->isCubeOp(MI.getOpcode());
178  if (!IsReduction && !IsVector && !IsCube) {
179  continue;
180  }
181 
182  // Expand the instruction
183  //
184  // Reduction instructions:
185  // T0_X = DP4 T1_XYZW, T2_XYZW
186  // becomes:
187  // TO_X = DP4 T1_X, T2_X
188  // TO_Y (write masked) = DP4 T1_Y, T2_Y
189  // TO_Z (write masked) = DP4 T1_Z, T2_Z
190  // TO_W (write masked) = DP4 T1_W, T2_W
191  //
192  // Vector instructions:
193  // T0_X = MULLO_INT T1_X, T2_X
194  // becomes:
195  // T0_X = MULLO_INT T1_X, T2_X
196  // T0_Y (write masked) = MULLO_INT T1_X, T2_X
197  // T0_Z (write masked) = MULLO_INT T1_X, T2_X
198  // T0_W (write masked) = MULLO_INT T1_X, T2_X
199  //
200  // Cube instructions:
201  // T0_XYZW = CUBE T1_XYZW
202  // becomes:
203  // TO_X = CUBE T1_Z, T1_Y
204  // T0_Y = CUBE T1_Z, T1_X
205  // T0_Z = CUBE T1_X, T1_Z
206  // T0_W = CUBE T1_Y, T1_Z
207  for (unsigned Chan = 0; Chan < 4; Chan++) {
208  Register DstReg =
209  MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
210  Register Src0 =
211  MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
212  unsigned Src1 = 0;
213 
214  // Determine the correct source registers
215  if (!IsCube) {
216  int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
217  if (Src1Idx != -1) {
218  Src1 = MI.getOperand(Src1Idx).getReg();
219  }
220  }
221  if (IsReduction) {
222  unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan);
223  Src0 = TRI.getSubReg(Src0, SubRegIndex);
224  Src1 = TRI.getSubReg(Src1, SubRegIndex);
225  } else if (IsCube) {
226  static const int CubeSrcSwz[] = {2, 2, 0, 1};
227  unsigned SubRegIndex0 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]);
228  unsigned SubRegIndex1 = AMDGPURegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
229  Src1 = TRI.getSubReg(Src0, SubRegIndex1);
230  Src0 = TRI.getSubReg(Src0, SubRegIndex0);
231  }
232 
233  // Determine the correct destination registers;
234  bool Mask = false;
235  bool NotLast = true;
236  if (IsCube) {
237  unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan);
238  DstReg = TRI.getSubReg(DstReg, SubRegIndex);
239  } else {
240  // Mask the write if the original instruction does not write to
241  // the current Channel.
242  Mask = (Chan != TRI.getHWRegChan(DstReg));
243  unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
244  DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
245  }
246 
247  // Set the IsLast bit
248  NotLast = (Chan != 3 );
249 
250  // Add the new instruction
251  unsigned Opcode = MI.getOpcode();
252  switch (Opcode) {
253  case R600::CUBE_r600_pseudo:
254  Opcode = R600::CUBE_r600_real;
255  break;
256  case R600::CUBE_eg_pseudo:
257  Opcode = R600::CUBE_eg_real;
258  break;
259  default:
260  break;
261  }
262 
263  MachineInstr *NewMI =
264  TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1);
265 
266  if (Chan != 0)
267  NewMI->bundleWithPred();
268  if (Mask) {
269  TII->addFlag(*NewMI, 0, MO_FLAG_MASK);
270  }
271  if (NotLast) {
272  TII->addFlag(*NewMI, 0, MO_FLAG_NOT_LAST);
273  }
274  SetFlagInNewMI(NewMI, &MI, R600::OpName::clamp);
275  SetFlagInNewMI(NewMI, &MI, R600::OpName::literal);
276  SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_abs);
277  SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_abs);
278  SetFlagInNewMI(NewMI, &MI, R600::OpName::src0_neg);
279  SetFlagInNewMI(NewMI, &MI, R600::OpName::src1_neg);
280  }
281  MI.eraseFromParent();
282  }
283  }
284  return false;
285 }
void bundleWithPred()
Bundle this instruction with its predecessor.
static unsigned getSubRegFromChannel(unsigned Channel)
AMDGPU specific subclass of TargetSubtarget.
This class represents lattice values for constants.
Definition: AllocatorList.h:23
Interface definition for R600InstrInfo.
unsigned const TargetRegisterInfo * TRI
Interface definition for R600RegisterInfo.
INITIALIZE_PASS_BEGIN(R600ExpandSpecialInstrsPass, DEBUG_TYPE, "R600 Expand Special Instrs", false, false) INITIALIZE_PASS_END(R600ExpandSpecialInstrsPass
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
void eraseFromParent()
Unlink &#39;this&#39; from the containing basic block and delete it.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:411
FunctionPass * createR600ExpandSpecialInstrsPass()
void setReg(Register Reg)
Change the register this operand corresponds to.
char & R600ExpandSpecialInstrsPassID
#define HW_REG_MASK
Defines for extracting register information from register encoding.
Definition: R600Defines.h:55
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
const R600InstrInfo * getInstrInfo() const override
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
const R600RegisterInfo * getRegisterInfo() const override
Iterator for intrusive lists based on ilist_node.
MachineOperand class - Representation of each machine instruction operand.
#define DEBUG_TYPE
int64_t getImm() const
unsigned getHWRegChan(unsigned reg) const
get the HW encoding for a register&#39;s channel.
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo)
Provides AMDGPU specific target descriptions.
Representation of each machine instruction.
Definition: MachineInstr.h:64
#define MO_FLAG_NOT_LAST
Definition: R600Defines.h:21
#define I(x, y, z)
Definition: MD5.cpp:58
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
#define MO_FLAG_MASK
Definition: R600Defines.h:19
Register getReg() const
getReg - Returns the register number.
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:416
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
#define MO_FLAG_PUSH
Definition: R600Defines.h:20