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24 bool isConstantLoad(
const MemSDNode *
N,
int cbID)
const;
46 #include "R600GenDAGISel.inc"
51 return SelectionDAGISel::runOnMachineFunction(
MF);
54 bool R600DAGToDAGISel::isConstantLoad(
const MemSDNode *
N,
int CbId)
const {
64 bool R600DAGToDAGISel::SelectGlobalValueConstantOffset(
SDValue Addr,
74 bool R600DAGToDAGISel::SelectGlobalValueVariableOffset(
SDValue Addr,
77 if (!isa<ConstantSDNode>(
Addr)) {
86 unsigned int Opc =
N->getOpcode();
87 if (
N->isMachineOpcode()) {
98 EVT VT =
N->getValueType(0);
105 switch (NumVectorElts) {
107 RegClassID = R600::R600_Reg64RegClassID;
111 RegClassID = R600::R600_Reg128VerticalRegClassID;
113 RegClassID = R600::R600_Reg128RegClassID;
131 if ((
C = dyn_cast<ConstantSDNode>(
Addr))) {
135 (
C = dyn_cast<ConstantSDNode>(
Addr.getOperand(0)))) {
139 (
C = dyn_cast<ConstantSDNode>(
Addr.getOperand(1)))) {
155 (IMMOffset = dyn_cast<ConstantSDNode>(
Addr.getOperand(1))) &&
163 }
else if ((IMMOffset = dyn_cast<ConstantSDNode>(
Addr)) &&
bool runOnMachineFunction(MachineFunction &MF) override
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
AMDGPU specific code to select AMDGPU machine instructions for SelectionDAG operations.
This is an abstract virtual class for memory operations.
void SelectBuildVector(SDNode *N, unsigned RegClassID)
SDValue getRegister(unsigned Reg, EVT VT)
(vector float) vec_cmpeq(*A, *B) C
CodeGenOpt::Level OptLevel
bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset) override
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
void Select(SDNode *N) override
Main hook for targets to transform nodes into machine nodes.
Common register allocation spilling lr str ldr sxth r3 ldr mla r4 can lr mov lr str ldr sxth r3 mla r4 and then merge mul and lr str ldr sxth r3 mla r4 It also increase the likelihood the store may become dead bb27 Successors according to LLVM ID Predecessors according to mbb< bb27, 0x8b0a7c0 > Note ADDri is not a two address instruction its result reg1037 is an operand of the PHI node in bb76 and its operand reg1039 is the result of the PHI node We should treat it as a two address code and make sure the ADDri is scheduled after any node that reads reg1039 Use info(i.e. register scavenger) to assign it a free register to allow reuse the collector could move the objects and invalidate the derived pointer This is bad enough in the first but safe points can crop up unpredictably **array_addr i32
@ BUILD_VERTICAL_VECTOR
This node is for VLIW targets and it is used to represent a vector that is stored in consecutive regi...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
Primary interface to the complete machine description for the target machine.
uint64_t getZExtValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
R600DAGToDAGISel(TargetMachine *TM, CodeGenOpt::Level OptLevel)
bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset) override
constexpr bool isInt< 16 >(int64_t x)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ ADD
Simple integer binary arithmetic operators.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
const char LLVMTargetMachineRef TM
FunctionPass class - This class is used to implement most global optimizations.
FunctionPass * createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a R600-specific.
void PreprocessISelDAG() override
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...