LLVM  11.0.0git
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1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Subclass of MipsTargetLowering specialized for mips32/64.
10 //
11 //===----------------------------------------------------------------------===//
16 #include "MipsISelLowering.h"
20 namespace llvm {
22 class MachineBasicBlock;
23 class MachineInstr;
24 class MipsSubtarget;
25 class MipsTargetMachine;
26 class SelectionDAG;
27 class TargetRegisterClass;
30  public:
31  explicit MipsSETargetLowering(const MipsTargetMachine &TM,
32  const MipsSubtarget &STI);
34  /// Enable MSA support for the given integer type and Register
35  /// class.
38  /// Enable MSA support for the given floating-point type and
39  /// Register class.
41  const TargetRegisterClass *RC);
44  EVT VT, unsigned AS = 0, unsigned Align = 1,
46  bool *Fast = nullptr) const override;
48  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
50  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
54  MachineBasicBlock *MBB) const override;
56  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override {
57  return false;
58  }
60  const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
62  private:
63  bool isEligibleForTailCallOptimization(
64  const CCState &CCInfo, unsigned NextStackOffset,
65  const MipsFunctionInfo &FI) const override;
67  void
68  getOpndList(SmallVectorImpl<SDValue> &Ops,
69  std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
70  bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
71  bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
72  SDValue Chain) const override;
74  SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
75  SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
76  SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
78  SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
79  SelectionDAG &DAG) const;
81  SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
82  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
83  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
84  SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
85  SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
86  /// Lower VECTOR_SHUFFLE into one of a number of instructions
87  /// depending on the indices in the shuffle.
88  SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
89  SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
91  MachineBasicBlock *emitBPOSGE32(MachineInstr &MI,
92  MachineBasicBlock *BB) const;
93  MachineBasicBlock *emitMSACBranchPseudo(MachineInstr &MI,
95  unsigned BranchOp) const;
96  /// Emit the COPY_FW pseudo instruction
97  MachineBasicBlock *emitCOPY_FW(MachineInstr &MI,
98  MachineBasicBlock *BB) const;
99  /// Emit the COPY_FD pseudo instruction
100  MachineBasicBlock *emitCOPY_FD(MachineInstr &MI,
101  MachineBasicBlock *BB) const;
102  /// Emit the INSERT_FW pseudo instruction
103  MachineBasicBlock *emitINSERT_FW(MachineInstr &MI,
104  MachineBasicBlock *BB) const;
105  /// Emit the INSERT_FD pseudo instruction
106  MachineBasicBlock *emitINSERT_FD(MachineInstr &MI,
107  MachineBasicBlock *BB) const;
108  /// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
109  MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr &MI,
110  MachineBasicBlock *BB,
111  unsigned EltSizeInBytes,
112  bool IsFP) const;
113  /// Emit the FILL_FW pseudo instruction
114  MachineBasicBlock *emitFILL_FW(MachineInstr &MI,
115  MachineBasicBlock *BB) const;
116  /// Emit the FILL_FD pseudo instruction
117  MachineBasicBlock *emitFILL_FD(MachineInstr &MI,
118  MachineBasicBlock *BB) const;
119  /// Emit the FEXP2_W_1 pseudo instructions.
120  MachineBasicBlock *emitFEXP2_W_1(MachineInstr &MI,
121  MachineBasicBlock *BB) const;
122  /// Emit the FEXP2_D_1 pseudo instructions.
123  MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI,
124  MachineBasicBlock *BB) const;
125  /// Emit the FILL_FW pseudo instruction
126  MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI,
127  MachineBasicBlock *BB) const;
128  /// Emit the FILL_FD pseudo instruction
129  MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI,
130  MachineBasicBlock *BB) const;
131  /// Emit the FEXP2_W_1 pseudo instructions.
132  MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI,
133  MachineBasicBlock *BB,
134  bool IsFGR64) const;
135  /// Emit the FEXP2_D_1 pseudo instructions.
136  MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI,
137  MachineBasicBlock *BBi,
138  bool IsFGR64) const;
139  };
141 } // end namespace llvm
This class represents lattice values for constants.
Definition: AllocatorList.h:23
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the &#39;usesCustomInserter&#39; fla...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations, those with specific masks.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:43
std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:80
Machine Value Type.
Extended Value Type.
Definition: ValueTypes.h:35
This structure contains all information that is necessary for lowering calls.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
CCState - This class holds information needed while lowering arguments and return values...
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:223
Represents one node in the SelectionDAG.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, unsigned Align=1, MachineMemOperand::Flags Flags=MachineMemOperand::MONone, bool *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
amdgpu Simplify well known AMD library false FunctionCallee Callee
Flags values. These may be or&#39;d together.
Representation of each machine instruction.
Definition: MachineInstr.h:62
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the &#39;representative&#39; register class for the specified value type.
#define N
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
IRTranslator LLVM IR MI
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.