13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H
46 unsigned *
Fast =
nullptr)
const override;
66 bool isEligibleForTailCallOptimization(
67 const CCState &CCInfo,
unsigned NextStackOffset,
72 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
73 bool IsPICCall,
bool GlobalOrExternal,
bool InternalLinkage,
74 bool IsCallReloc, CallLoweringInfo &CLI,
SDValue Callee,
98 unsigned BranchOp)
const;
114 unsigned EltSizeInBytes,
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
static SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG)
static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, const RISCVSubtarget &Subtarget)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
CCState - This class holds information needed while lowering arguments and return values.
Representation of each machine instruction.
Flags
Flags values. These may be or'd together.
MipsFunctionInfo - This class is derived from MachineFunction private Mips target-specific informatio...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given floating-point type and Register class.
void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC)
Enable MSA support for the given integer type and Register class.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
const TargetRegisterClass * getRepRegClassFor(MVT VT) const override
Return the 'representative' register class for the specified value type.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const override
Determine if the target supports unaligned memory accesses.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
MipsSETargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
MipsTargetLowering(const MipsTargetMachine &TM, const MipsSubtarget &STI)
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
@ Fast
Attempts to make calls as fast as possible (e.g.
This is an optimization pass for GlobalISel generic memory operations.
DWARFExpression::Operation Op
This struct is a compact representation of a valid (non-zero power of two) alignment.