30#define DEBUG_TYPE "loongarch"
46 cl::desc(
"Enable the pass that removes dead"
47 " definitons and replaces stores to"
48 " them with stores to r0"),
53 cl::desc(
"Enable the loop data prefetch pass"),
58 return "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128";
59 assert(TT.isArch32Bit() &&
"only LA32 and LA64 are currently supported");
60 return "e-m:e-p:32:32-i64:64-n32-S128";
64 std::optional<Reloc::Model> RM) {
70 std::optional<CodeModel::Model> CM) {
79 if (!TT.isArch64Bit())
84 "Only small, medium and large code models are allowed on LoongArch");
103 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
104 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
105 Attribute FSAttr =
F.getFnAttribute(
"target-features");
109 std::string TuneCPU =
114 std::string Key = CPU + TuneCPU + FS;
115 auto &
I = SubtargetMap[Key];
122 if (
const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
123 F.getParent()->getModuleFlag(
"target-abi"))) {
126 ModuleTargetABI->getString() != ABIName) {
129 ABIName = ModuleTargetABI->getString();
131 I = std::make_unique<LoongArchSubtarget>(
TargetTriple, CPU, TuneCPU, FS,
140 return LoongArchMachineFunctionInfo::create<LoongArchMachineFunctionInfo>(
151 return getTM<LoongArchTargetMachine>();
154 void addIRPasses()
override;
155 void addCodeGenPrepare()
override;
156 bool addInstSelector()
override;
157 void addPreEmitPass()
override;
158 void addPreEmitPass2()
override;
159 void addMachineSSAOptimization()
override;
160 void addPreRegAlloc()
override;
161 bool addRegAssignAndRewriteFast()
override;
162 bool addRegAssignAndRewriteOptimized()
override;
168 return new LoongArchPassConfig(*
this, PM);
171void LoongArchPassConfig::addIRPasses() {
183void LoongArchPassConfig::addCodeGenPrepare() {
189bool LoongArchPassConfig::addInstSelector() {
202void LoongArchPassConfig::addPreEmitPass2() {
210void LoongArchPassConfig::addMachineSSAOptimization() {
213 if (
TM->getTargetTriple().isLoongArch64()) {
218void LoongArchPassConfig::addPreRegAlloc() {
224bool LoongArchPassConfig::addRegAssignAndRewriteFast() {
231bool LoongArchPassConfig::addRegAssignAndRewriteOptimized() {
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::string computeDataLayout()
static cl::opt< bool > EnableLoongArchDeadRegisterElimination("loongarch-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to r0"), cl::init(true))
static cl::opt< bool > EnableLoopDataPrefetch("loongarch-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(false))
static CodeModel::Model getEffectiveLoongArchCodeModel(const Triple &TT, std::optional< CodeModel::Model > CM)
static Reloc::Model getEffectiveRelocModel(const Triple &TT, std::optional< Reloc::Model > RM)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLoongArchTarget()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
Target-Independent Code Generator Pass Configuration Options pass.
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
LoongArchTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
~LoongArchTargetMachine() override
const LoongArchSubtarget * getSubtargetImpl() const =delete
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
MCTargetOptions MCOptions
Machine level options.
Target-Independent Code Generator Pass Configuration Options.
virtual void addCodeGenPrepare()
Add pass to prepare the LLVM IR for code generation.
virtual bool addRegAssignAndRewriteFast()
Add core register allocator passes which do the actual register assignment and rewriting.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
ABI getTargetABI(StringRef ABIName)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
Target & getTheLoongArch64Target()
FunctionPass * createLoongArchExpandAtomicPseudoPass()
FunctionPass * createLoongArchDeadRegisterDefinitionsPass()
void initializeLoongArchDAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createTypePromotionLegacyPass()
Create IR Type Promotion pass.
void initializeLoongArchPreRAExpandPseudoPass(PassRegistry &)
FunctionPass * createLoongArchISelDag(LoongArchTargetMachine &TM)
void initializeLoongArchMergeBaseOffsetOptPass(PassRegistry &)
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
FunctionPass * createLoongArchOptWInstrsPass()
FunctionPass * createLoopDataPrefetchPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
CodeGenOptLevel
Code generation optimization level.
Target & getTheLoongArch32Target()
FunctionPass * createLoongArchPreRAExpandPseudoPass()
void initializeLoongArchOptWInstrsPass(PassRegistry &)
FunctionPass * createLoongArchExpandPseudoPass()
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
void initializeLoongArchDeadRegisterDefinitionsPass(PassRegistry &)
FunctionPass * createLoongArchMergeBaseOffsetOptPass()
Returns an instance of the Merge Base Offset Optimization pass.
Implement std::hash so that hash_code can be used in STL containers.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
RegisterTargetMachine - Helper template for registering a target machine implementation,...