LLVM 18.0.0git
SystemZTargetMachine.cpp
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1//===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
11#include "SystemZ.h"
16#include "llvm/ADT/StringRef.h"
18#include "llvm/CodeGen/Passes.h"
21#include "llvm/IR/DataLayout.h"
26#include <memory>
27#include <optional>
28#include <string>
29
30using namespace llvm;
31
32// NOLINTNEXTLINE(readability-identifier-naming)
34 // Register the target.
45}
46
47static std::string computeDataLayout(const Triple &TT) {
48 std::string Ret;
49
50 // Big endian.
51 Ret += "E";
52
53 // Data mangling.
55
56 // Make sure that global data has at least 16 bits of alignment by
57 // default, so that we can refer to it using LARL. We don't have any
58 // special requirements for stack variables though.
59 Ret += "-i1:8:16-i8:8:16";
60
61 // 64-bit integers are naturally aligned.
62 Ret += "-i64:64";
63
64 // 128-bit floats are aligned only to 64 bits.
65 Ret += "-f128:64";
66
67 // The DataLayout string always holds a vector alignment of 64 bits, see
68 // comment in clang/lib/Basic/Targets/SystemZ.h.
69 Ret += "-v128:64";
70
71 // We prefer 16 bits of aligned for all globals; see above.
72 Ret += "-a:8:16";
73
74 // Integer registers are 32 or 64 bits.
75 Ret += "-n32:64";
76
77 return Ret;
78}
79
80static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
81 if (TT.isOSzOS())
82 return std::make_unique<TargetLoweringObjectFileGOFF>();
83
84 // Note: Some times run with -triple s390x-unknown.
85 // In this case, default to ELF unless z/OS specifically provided.
86 return std::make_unique<TargetLoweringObjectFileELF>();
87}
88
89static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
90 // Static code is suitable for use in a dynamic executable; there is no
91 // separate DynamicNoPIC model.
92 if (!RM || *RM == Reloc::DynamicNoPIC)
93 return Reloc::Static;
94 return *RM;
95}
96
97// For SystemZ we define the models as follows:
98//
99// Small: BRASL can call any function and will use a stub if necessary.
100// Locally-binding symbols will always be in range of LARL.
101//
102// Medium: BRASL can call any function and will use a stub if necessary.
103// GOT slots and locally-defined text will always be in range
104// of LARL, but other symbols might not be.
105//
106// Large: Equivalent to Medium for now.
107//
108// Kernel: Equivalent to Medium for now.
109//
110// This means that any PIC module smaller than 4GB meets the
111// requirements of Small, so Small seems like the best default there.
112//
113// All symbols bind locally in a non-PIC module, so the choice is less
114// obvious. There are two cases:
115//
116// - When creating an executable, PLTs and copy relocations allow
117// us to treat external symbols as part of the executable.
118// Any executable smaller than 4GB meets the requirements of Small,
119// so that seems like the best default.
120//
121// - When creating JIT code, stubs will be in range of BRASL if the
122// image is less than 4GB in size. GOT entries will likewise be
123// in range of LARL. However, the JIT environment has no equivalent
124// of copy relocs, so locally-binding data symbols might not be in
125// the range of LARL. We need the Medium model in that case.
126static CodeModel::Model
127getEffectiveSystemZCodeModel(std::optional<CodeModel::Model> CM,
128 Reloc::Model RM, bool JIT) {
129 if (CM) {
130 if (*CM == CodeModel::Tiny)
131 report_fatal_error("Target does not support the tiny CodeModel", false);
132 if (*CM == CodeModel::Kernel)
133 report_fatal_error("Target does not support the kernel CodeModel", false);
134 return *CM;
135 }
136 if (JIT)
138 return CodeModel::Small;
139}
140
142 StringRef CPU, StringRef FS,
143 const TargetOptions &Options,
144 std::optional<Reloc::Model> RM,
145 std::optional<CodeModel::Model> CM,
146 CodeGenOptLevel OL, bool JIT)
148 T, computeDataLayout(TT), TT, CPU, FS, Options,
151 OL),
152 TLOF(createTLOF(getTargetTriple())) {
153 initAsmInfo();
154}
155
157
158const SystemZSubtarget *
160 Attribute CPUAttr = F.getFnAttribute("target-cpu");
161 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
162 Attribute FSAttr = F.getFnAttribute("target-features");
163
164 std::string CPU =
165 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
166 std::string TuneCPU =
167 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
168 std::string FS =
169 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
170
171 // FIXME: This is related to the code below to reset the target options,
172 // we need to know whether the soft float and backchain flags are set on the
173 // function, so we can enable them as subtarget features.
174 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
175 if (SoftFloat)
176 FS += FS.empty() ? "+soft-float" : ",+soft-float";
177 bool BackChain = F.hasFnAttribute("backchain");
178 if (BackChain)
179 FS += FS.empty() ? "+backchain" : ",+backchain";
180
181 auto &I = SubtargetMap[CPU + TuneCPU + FS];
182 if (!I) {
183 // This needs to be done before we create a new subtarget since any
184 // creation will depend on the TM and the code generation flags on the
185 // function that reside in TargetOptions.
187 I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, TuneCPU, FS,
188 *this);
189 }
190
191 return I.get();
192}
193
194namespace {
195
196/// SystemZ Code Generator Pass Configuration Options.
197class SystemZPassConfig : public TargetPassConfig {
198public:
199 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
200 : TargetPassConfig(TM, PM) {}
201
202 SystemZTargetMachine &getSystemZTargetMachine() const {
203 return getTM<SystemZTargetMachine>();
204 }
205
207 createPostMachineScheduler(MachineSchedContext *C) const override {
208 return new ScheduleDAGMI(C,
209 std::make_unique<SystemZPostRASchedStrategy>(C),
210 /*RemoveKillFlags=*/true);
211 }
212
213 void addIRPasses() override;
214 bool addInstSelector() override;
215 bool addILPOpts() override;
216 void addPreRegAlloc() override;
217 void addPostRewrite() override;
218 void addPostRegAlloc() override;
219 void addPreSched2() override;
220 void addPreEmitPass() override;
221};
222
223} // end anonymous namespace
224
225void SystemZPassConfig::addIRPasses() {
226 if (getOptLevel() != CodeGenOptLevel::None) {
227 addPass(createSystemZTDCPass());
229 }
230
231 addPass(createAtomicExpandPass());
232
234}
235
236bool SystemZPassConfig::addInstSelector() {
237 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
238
239 if (getOptLevel() != CodeGenOptLevel::None)
240 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
241
242 return false;
243}
244
245bool SystemZPassConfig::addILPOpts() {
246 addPass(&EarlyIfConverterID);
247 return true;
248}
249
250void SystemZPassConfig::addPreRegAlloc() {
251 addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine()));
252}
253
254void SystemZPassConfig::addPostRewrite() {
255 addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
256}
257
258void SystemZPassConfig::addPostRegAlloc() {
259 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
260 // is not called).
261 if (getOptLevel() == CodeGenOptLevel::None)
262 addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
263}
264
265void SystemZPassConfig::addPreSched2() {
266 if (getOptLevel() != CodeGenOptLevel::None)
267 addPass(&IfConverterID);
268}
269
270void SystemZPassConfig::addPreEmitPass() {
271 // Do instruction shortening before compare elimination because some
272 // vector instructions will be shortened into opcodes that compare
273 // elimination recognizes.
274 if (getOptLevel() != CodeGenOptLevel::None)
275 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
276
277 // We eliminate comparisons here rather than earlier because some
278 // transformations can change the set of available CC values and we
279 // generally want those transformations to have priority. This is
280 // especially true in the commonest case where the result of the comparison
281 // is used by a single in-range branch instruction, since we will then
282 // be able to fuse the compare and the branch instead.
283 //
284 // For example, two-address NILF can sometimes be converted into
285 // three-address RISBLG. NILF produces a CC value that indicates whether
286 // the low word is zero, but RISBLG does not modify CC at all. On the
287 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
288 // The CC value produced by NILL isn't useful for our purposes, but the
289 // value produced by RISBG can be used for any comparison with zero
290 // (not just equality). So there are some transformations that lose
291 // CC values (while still being worthwhile) and others that happen to make
292 // the CC result more useful than it was originally.
293 //
294 // Another reason is that we only want to use BRANCH ON COUNT in cases
295 // where we know that the count register is not going to be spilled.
296 //
297 // Doing it so late makes it more likely that a register will be reused
298 // between the comparison and the branch, but it isn't clear whether
299 // preventing that would be a win or not.
300 if (getOptLevel() != CodeGenOptLevel::None)
301 addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
302 addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
303
304 // Do final scheduling after all other optimizations, to get an
305 // optimal input for the decoder (branch relaxation must happen
306 // after block placement).
307 if (getOptLevel() != CodeGenOptLevel::None)
308 addPass(&PostMachineSchedulerID);
309}
310
312 return new SystemZPassConfig(*this, PM);
313}
314
317 return TargetTransformInfo(SystemZTTIImpl(this, F));
318}
319
321 BumpPtrAllocator &Allocator, const Function &F,
322 const TargetSubtargetInfo *STI) const {
323 return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>(
324 Allocator, F, STI);
325}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
const char LLVMTargetMachineRef TM
Basic Register Allocator
static CodeModel::Model getEffectiveSystemZCodeModel(std::optional< CodeModel::Model > CM, Reloc::Model RM, bool JIT)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget()
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
This class describes a target machine that is implemented with the LLVM target-independent code gener...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
const SystemZSubtarget * getSubtargetImpl() const =delete
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSystemZTarget()
void initializeSystemZElimComparePass(PassRegistry &)
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOptLevel OptLevel)
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM)
FunctionPass * createSystemZElimComparePass(SystemZTargetMachine &TM)
void initializeSystemZDAGToDAGISelPass(PassRegistry &)
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
void initializeSystemZLongBranchPass(PassRegistry &)
void initializeSystemZShortenInstPass(PassRegistry &)
FunctionPass * createSystemZTDCPass()
FunctionPass * createLoopDataPrefetchPass()
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
void initializeSystemZPostRewritePass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
void initializeSystemZTDCPassPass(PassRegistry &)
FunctionPass * createSystemZLDCleanupPass(SystemZTargetMachine &TM)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createSystemZPostRewritePass(SystemZTargetMachine &TM)
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
void initializeSystemZLDCleanupPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...