LLVM  14.0.0git
SystemZTargetMachine.cpp
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1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZTargetMachine.h"
11 #include "SystemZ.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/MC/TargetRegistry.h"
25 #include "llvm/Support/CodeGen.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include <string>
29 
30 using namespace llvm;
31 
33  // Register the target.
35  auto &PR = *PassRegistry::getPassRegistry();
43 }
44 
45 // Determine whether we use the vector ABI.
46 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
47  // We use the vector ABI whenever the vector facility is avaiable.
48  // This is the case by default if CPU is z13 or later, and can be
49  // overridden via "[+-]vector" feature string elements.
50  bool VectorABI = true;
51  bool SoftFloat = false;
52  if (CPU.empty() || CPU == "generic" ||
53  CPU == "z10" || CPU == "z196" || CPU == "zEC12" ||
54  CPU == "arch8" || CPU == "arch9" || CPU == "arch10")
55  VectorABI = false;
56 
58  FS.split(Features, ',', -1, false /* KeepEmpty */);
59  for (auto &Feature : Features) {
60  if (Feature == "vector" || Feature == "+vector")
61  VectorABI = true;
62  if (Feature == "-vector")
63  VectorABI = false;
64  if (Feature == "soft-float" || Feature == "+soft-float")
65  SoftFloat = true;
66  if (Feature == "-soft-float")
67  SoftFloat = false;
68  }
69 
70  return VectorABI && !SoftFloat;
71 }
72 
73 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
74  StringRef FS) {
75  bool VectorABI = UsesVectorABI(CPU, FS);
76  std::string Ret;
77 
78  // Big endian.
79  Ret += "E";
80 
81  // Data mangling.
83 
84  // Make sure that global data has at least 16 bits of alignment by
85  // default, so that we can refer to it using LARL. We don't have any
86  // special requirements for stack variables though.
87  Ret += "-i1:8:16-i8:8:16";
88 
89  // 64-bit integers are naturally aligned.
90  Ret += "-i64:64";
91 
92  // 128-bit floats are aligned only to 64 bits.
93  Ret += "-f128:64";
94 
95  // When using the vector ABI on Linux, 128-bit vectors are also aligned to 64
96  // bits. On z/OS, vector types are always aligned to 64 bits.
97  if (VectorABI || TT.isOSzOS())
98  Ret += "-v128:64";
99 
100  // We prefer 16 bits of aligned for all globals; see above.
101  Ret += "-a:8:16";
102 
103  // Integer registers are 32 or 64 bits.
104  Ret += "-n32:64";
105 
106  return Ret;
107 }
108 
109 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
110  if (TT.isOSzOS())
111  return std::make_unique<TargetLoweringObjectFileGOFF>();
112 
113  // Note: Some times run with -triple s390x-unknown.
114  // In this case, default to ELF unless z/OS specifically provided.
115  return std::make_unique<TargetLoweringObjectFileELF>();
116 }
117 
119  // Static code is suitable for use in a dynamic executable; there is no
120  // separate DynamicNoPIC model.
121  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
122  return Reloc::Static;
123  return *RM;
124 }
125 
126 // For SystemZ we define the models as follows:
127 //
128 // Small: BRASL can call any function and will use a stub if necessary.
129 // Locally-binding symbols will always be in range of LARL.
130 //
131 // Medium: BRASL can call any function and will use a stub if necessary.
132 // GOT slots and locally-defined text will always be in range
133 // of LARL, but other symbols might not be.
134 //
135 // Large: Equivalent to Medium for now.
136 //
137 // Kernel: Equivalent to Medium for now.
138 //
139 // This means that any PIC module smaller than 4GB meets the
140 // requirements of Small, so Small seems like the best default there.
141 //
142 // All symbols bind locally in a non-PIC module, so the choice is less
143 // obvious. There are two cases:
144 //
145 // - When creating an executable, PLTs and copy relocations allow
146 // us to treat external symbols as part of the executable.
147 // Any executable smaller than 4GB meets the requirements of Small,
148 // so that seems like the best default.
149 //
150 // - When creating JIT code, stubs will be in range of BRASL if the
151 // image is less than 4GB in size. GOT entries will likewise be
152 // in range of LARL. However, the JIT environment has no equivalent
153 // of copy relocs, so locally-binding data symbols might not be in
154 // the range of LARL. We need the Medium model in that case.
155 static CodeModel::Model
157  bool JIT) {
158  if (CM) {
159  if (*CM == CodeModel::Tiny)
160  report_fatal_error("Target does not support the tiny CodeModel", false);
161  if (*CM == CodeModel::Kernel)
162  report_fatal_error("Target does not support the kernel CodeModel", false);
163  return *CM;
164  }
165  if (JIT)
167  return CodeModel::Small;
168 }
169 
171  StringRef CPU, StringRef FS,
172  const TargetOptions &Options,
175  CodeGenOpt::Level OL, bool JIT)
177  T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
180  OL),
181  TLOF(createTLOF(getTargetTriple())) {
182  initAsmInfo();
183 }
184 
186 
187 const SystemZSubtarget *
189  Attribute CPUAttr = F.getFnAttribute("target-cpu");
190  Attribute FSAttr = F.getFnAttribute("target-features");
191 
192  std::string CPU =
193  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
194  std::string FS =
195  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
196 
197  // FIXME: This is related to the code below to reset the target options,
198  // we need to know whether or not the soft float flag is set on the
199  // function, so we can enable it as a subtarget feature.
200  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
201 
202  if (softFloat)
203  FS += FS.empty() ? "+soft-float" : ",+soft-float";
204 
205  auto &I = SubtargetMap[CPU + FS];
206  if (!I) {
207  // This needs to be done before we create a new subtarget since any
208  // creation will depend on the TM and the code generation flags on the
209  // function that reside in TargetOptions.
211  I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, FS, *this);
212  }
213 
214  return I.get();
215 }
216 
217 namespace {
218 
219 /// SystemZ Code Generator Pass Configuration Options.
220 class SystemZPassConfig : public TargetPassConfig {
221 public:
222  SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
223  : TargetPassConfig(TM, PM) {}
224 
225  SystemZTargetMachine &getSystemZTargetMachine() const {
226  return getTM<SystemZTargetMachine>();
227  }
228 
230  createPostMachineScheduler(MachineSchedContext *C) const override {
231  return new ScheduleDAGMI(C,
232  std::make_unique<SystemZPostRASchedStrategy>(C),
233  /*RemoveKillFlags=*/true);
234  }
235 
236  void addIRPasses() override;
237  bool addInstSelector() override;
238  bool addILPOpts() override;
239  void addPreRegAlloc() override;
240  void addPostRewrite() override;
241  void addPostRegAlloc() override;
242  void addPreSched2() override;
243  void addPreEmitPass() override;
244 };
245 
246 } // end anonymous namespace
247 
248 void SystemZPassConfig::addIRPasses() {
249  if (getOptLevel() != CodeGenOpt::None) {
250  addPass(createSystemZTDCPass());
251  addPass(createLoopDataPrefetchPass());
252  }
253 
255 }
256 
257 bool SystemZPassConfig::addInstSelector() {
258  addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
259 
260  if (getOptLevel() != CodeGenOpt::None)
261  addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
262 
263  return false;
264 }
265 
266 bool SystemZPassConfig::addILPOpts() {
267  addPass(&EarlyIfConverterID);
268  return true;
269 }
270 
271 void SystemZPassConfig::addPreRegAlloc() {
272  addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine()));
273 }
274 
275 void SystemZPassConfig::addPostRewrite() {
276  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
277 }
278 
279 void SystemZPassConfig::addPostRegAlloc() {
280  // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
281  // is not called).
282  if (getOptLevel() == CodeGenOpt::None)
283  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
284 }
285 
286 void SystemZPassConfig::addPreSched2() {
287  if (getOptLevel() != CodeGenOpt::None)
288  addPass(&IfConverterID);
289 }
290 
291 void SystemZPassConfig::addPreEmitPass() {
292  // Do instruction shortening before compare elimination because some
293  // vector instructions will be shortened into opcodes that compare
294  // elimination recognizes.
295  if (getOptLevel() != CodeGenOpt::None)
296  addPass(createSystemZShortenInstPass(getSystemZTargetMachine()));
297 
298  // We eliminate comparisons here rather than earlier because some
299  // transformations can change the set of available CC values and we
300  // generally want those transformations to have priority. This is
301  // especially true in the commonest case where the result of the comparison
302  // is used by a single in-range branch instruction, since we will then
303  // be able to fuse the compare and the branch instead.
304  //
305  // For example, two-address NILF can sometimes be converted into
306  // three-address RISBLG. NILF produces a CC value that indicates whether
307  // the low word is zero, but RISBLG does not modify CC at all. On the
308  // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
309  // The CC value produced by NILL isn't useful for our purposes, but the
310  // value produced by RISBG can be used for any comparison with zero
311  // (not just equality). So there are some transformations that lose
312  // CC values (while still being worthwhile) and others that happen to make
313  // the CC result more useful than it was originally.
314  //
315  // Another reason is that we only want to use BRANCH ON COUNT in cases
316  // where we know that the count register is not going to be spilled.
317  //
318  // Doing it so late makes it more likely that a register will be reused
319  // between the comparison and the branch, but it isn't clear whether
320  // preventing that would be a win or not.
321  if (getOptLevel() != CodeGenOpt::None)
322  addPass(createSystemZElimComparePass(getSystemZTargetMachine()));
323  addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
324 
325  // Do final scheduling after all other optimizations, to get an
326  // optimal input for the decoder (branch relaxation must happen
327  // after block placement).
328  if (getOptLevel() != CodeGenOpt::None)
329  addPass(&PostMachineSchedulerID);
330 }
331 
333  return new SystemZPassConfig(*this, PM);
334 }
335 
338  return TargetTransformInfo(SystemZTTIImpl(this, F));
339 }
llvm::initializeSystemZLDCleanupPass
void initializeSystemZLDCleanupPass(PassRegistry &)
llvm::createSystemZLongBranchPass
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
Definition: SystemZLongBranch.cpp:485
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:22
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:168
Optional.h
llvm::X86AS::FS
@ FS
Definition: X86.h:188
UsesVectorABI
static bool UsesVectorABI(StringRef CPU, StringRef FS)
Definition: SystemZTargetMachine.cpp:46
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::Function
Definition: Function.h:62
llvm::Attribute
Definition: Attributes.h:52
StringRef.h
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1176
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::createSystemZISelDag
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: SystemZISelDAGToDAG.cpp:381
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
getEffectiveSystemZCodeModel
static CodeModel::Model getEffectiveSystemZCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool JIT)
Definition: SystemZTargetMachine.cpp:156
llvm::initializeSystemZPostRewritePass
void initializeSystemZPostRewritePass(PassRegistry &)
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:152
llvm::Optional< Reloc::Model >
SystemZMCTargetDesc.h
llvm::SystemZTargetMachine::~SystemZTargetMachine
~SystemZTargetMachine() override
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
SystemZTargetInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::initializeSystemZLongBranchPass
void initializeSystemZLongBranchPass(PassRegistry &)
llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createSystemZShortenInstPass
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
SystemZ.h
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:101
llvm::SystemZTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: SystemZTargetMachine.cpp:337
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:99
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: SystemZTargetMachine.cpp:109
SystemZTargetMachine.h
llvm::StringRef::empty
constexpr LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:133
llvm::createSystemZElimComparePass
FunctionPass * createSystemZElimComparePass(SystemZTargetMachine &TM)
Definition: SystemZElimCompare.cpp:748
LLVMInitializeSystemZTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget()
Definition: SystemZTargetMachine.cpp:32
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::SystemZTargetMachine
Definition: SystemZTargetMachine.h:27
TargetPassConfig.h
SystemZTargetTransformInfo.h
llvm::SystemZTargetMachine::getSubtargetImpl
const SystemZSubtarget * getSubtargetImpl() const =delete
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::SystemZTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: SystemZTargetMachine.cpp:332
llvm::SystemZTTIImpl
Definition: SystemZTargetTransformInfo.h:18
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:483
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS)
Definition: SystemZTargetMachine.cpp:73
llvm::createSystemZTDCPass
FunctionPass * createSystemZTDCPass()
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::SystemZTargetMachine::SystemZTargetMachine
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SystemZTargetMachine.cpp:170
llvm::initializeSystemZTDCPassPass
void initializeSystemZTDCPassPass(PassRegistry &)
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
CodeGen.h
SmallVector.h
llvm::initializeSystemZShortenInstPass
void initializeSystemZShortenInstPass(PassRegistry &)
llvm::initializeSystemZElimComparePass
void initializeSystemZElimComparePass(PassRegistry &)
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::createSystemZPostRewritePass
FunctionPass * createSystemZPostRewritePass(SystemZTargetMachine &TM)
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:245
llvm::createSystemZCopyPhysRegsPass
FunctionPass * createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM)
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::createSystemZLDCleanupPass
FunctionPass * createSystemZLDCleanupPass(SystemZTargetMachine &TM)
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:100
SystemZMachineScheduler.h
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:155
TargetLoweringObjectFileImpl.h