LLVM  14.0.0git
SystemZTargetMachine.cpp
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1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZTargetMachine.h"
11 #include "SystemZ.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/Passes.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Support/CodeGen.h"
27 #include "llvm/Transforms/Scalar.h"
28 #include <string>
29 
30 using namespace llvm;
31 
33  // Register the target.
35 }
36 
37 // Determine whether we use the vector ABI.
38 static bool UsesVectorABI(StringRef CPU, StringRef FS) {
39  // We use the vector ABI whenever the vector facility is avaiable.
40  // This is the case by default if CPU is z13 or later, and can be
41  // overridden via "[+-]vector" feature string elements.
42  bool VectorABI = true;
43  bool SoftFloat = false;
44  if (CPU.empty() || CPU == "generic" ||
45  CPU == "z10" || CPU == "z196" || CPU == "zEC12" ||
46  CPU == "arch8" || CPU == "arch9" || CPU == "arch10")
47  VectorABI = false;
48 
50  FS.split(Features, ',', -1, false /* KeepEmpty */);
51  for (auto &Feature : Features) {
52  if (Feature == "vector" || Feature == "+vector")
53  VectorABI = true;
54  if (Feature == "-vector")
55  VectorABI = false;
56  if (Feature == "soft-float" || Feature == "+soft-float")
57  SoftFloat = true;
58  if (Feature == "-soft-float")
59  SoftFloat = false;
60  }
61 
62  return VectorABI && !SoftFloat;
63 }
64 
65 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
66  StringRef FS) {
67  bool VectorABI = UsesVectorABI(CPU, FS);
68  std::string Ret;
69 
70  // Big endian.
71  Ret += "E";
72 
73  // Data mangling.
75 
76  // Make sure that global data has at least 16 bits of alignment by
77  // default, so that we can refer to it using LARL. We don't have any
78  // special requirements for stack variables though.
79  Ret += "-i1:8:16-i8:8:16";
80 
81  // 64-bit integers are naturally aligned.
82  Ret += "-i64:64";
83 
84  // 128-bit floats are aligned only to 64 bits.
85  Ret += "-f128:64";
86 
87  // When using the vector ABI, 128-bit vectors are also aligned to 64 bits.
88  if (VectorABI)
89  Ret += "-v128:64";
90 
91  // We prefer 16 bits of aligned for all globals; see above.
92  Ret += "-a:8:16";
93 
94  // Integer registers are 32 or 64 bits.
95  Ret += "-n32:64";
96 
97  return Ret;
98 }
99 
100 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
101  if (TT.isOSzOS())
102  return std::make_unique<TargetLoweringObjectFileGOFF>();
103 
104  // Note: Some times run with -triple s390x-unknown.
105  // In this case, default to ELF unless z/OS specifically provided.
106  return std::make_unique<TargetLoweringObjectFileELF>();
107 }
108 
110  // Static code is suitable for use in a dynamic executable; there is no
111  // separate DynamicNoPIC model.
112  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
113  return Reloc::Static;
114  return *RM;
115 }
116 
117 // For SystemZ we define the models as follows:
118 //
119 // Small: BRASL can call any function and will use a stub if necessary.
120 // Locally-binding symbols will always be in range of LARL.
121 //
122 // Medium: BRASL can call any function and will use a stub if necessary.
123 // GOT slots and locally-defined text will always be in range
124 // of LARL, but other symbols might not be.
125 //
126 // Large: Equivalent to Medium for now.
127 //
128 // Kernel: Equivalent to Medium for now.
129 //
130 // This means that any PIC module smaller than 4GB meets the
131 // requirements of Small, so Small seems like the best default there.
132 //
133 // All symbols bind locally in a non-PIC module, so the choice is less
134 // obvious. There are two cases:
135 //
136 // - When creating an executable, PLTs and copy relocations allow
137 // us to treat external symbols as part of the executable.
138 // Any executable smaller than 4GB meets the requirements of Small,
139 // so that seems like the best default.
140 //
141 // - When creating JIT code, stubs will be in range of BRASL if the
142 // image is less than 4GB in size. GOT entries will likewise be
143 // in range of LARL. However, the JIT environment has no equivalent
144 // of copy relocs, so locally-binding data symbols might not be in
145 // the range of LARL. We need the Medium model in that case.
146 static CodeModel::Model
148  bool JIT) {
149  if (CM) {
150  if (*CM == CodeModel::Tiny)
151  report_fatal_error("Target does not support the tiny CodeModel", false);
152  if (*CM == CodeModel::Kernel)
153  report_fatal_error("Target does not support the kernel CodeModel", false);
154  return *CM;
155  }
156  if (JIT)
158  return CodeModel::Small;
159 }
160 
162  StringRef CPU, StringRef FS,
163  const TargetOptions &Options,
166  CodeGenOpt::Level OL, bool JIT)
168  T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options,
171  OL),
172  TLOF(createTLOF(getTargetTriple())) {
173  initAsmInfo();
174 }
175 
177 
178 const SystemZSubtarget *
180  Attribute CPUAttr = F.getFnAttribute("target-cpu");
181  Attribute FSAttr = F.getFnAttribute("target-features");
182 
183  std::string CPU =
184  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
185  std::string FS =
186  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
187 
188  // FIXME: This is related to the code below to reset the target options,
189  // we need to know whether or not the soft float flag is set on the
190  // function, so we can enable it as a subtarget feature.
191  bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
192 
193  if (softFloat)
194  FS += FS.empty() ? "+soft-float" : ",+soft-float";
195 
196  auto &I = SubtargetMap[CPU + FS];
197  if (!I) {
198  // This needs to be done before we create a new subtarget since any
199  // creation will depend on the TM and the code generation flags on the
200  // function that reside in TargetOptions.
202  I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, FS, *this);
203  }
204 
205  return I.get();
206 }
207 
208 namespace {
209 
210 /// SystemZ Code Generator Pass Configuration Options.
211 class SystemZPassConfig : public TargetPassConfig {
212 public:
213  SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
214  : TargetPassConfig(TM, PM) {}
215 
216  SystemZTargetMachine &getSystemZTargetMachine() const {
217  return getTM<SystemZTargetMachine>();
218  }
219 
221  createPostMachineScheduler(MachineSchedContext *C) const override {
222  return new ScheduleDAGMI(C,
223  std::make_unique<SystemZPostRASchedStrategy>(C),
224  /*RemoveKillFlags=*/true);
225  }
226 
227  void addIRPasses() override;
228  bool addInstSelector() override;
229  bool addILPOpts() override;
230  void addPreRegAlloc() override;
231  void addPostRewrite() override;
232  void addPostRegAlloc() override;
233  void addPreSched2() override;
234  void addPreEmitPass() override;
235 };
236 
237 } // end anonymous namespace
238 
239 void SystemZPassConfig::addIRPasses() {
240  if (getOptLevel() != CodeGenOpt::None) {
241  addPass(createSystemZTDCPass());
242  addPass(createLoopDataPrefetchPass());
243  }
244 
246 }
247 
248 bool SystemZPassConfig::addInstSelector() {
249  addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel()));
250 
251  if (getOptLevel() != CodeGenOpt::None)
252  addPass(createSystemZLDCleanupPass(getSystemZTargetMachine()));
253 
254  return false;
255 }
256 
257 bool SystemZPassConfig::addILPOpts() {
258  addPass(&EarlyIfConverterID);
259  return true;
260 }
261 
262 void SystemZPassConfig::addPreRegAlloc() {
263  addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine()));
264 }
265 
266 void SystemZPassConfig::addPostRewrite() {
267  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
268 }
269 
270 void SystemZPassConfig::addPostRegAlloc() {
271  // PostRewrite needs to be run at -O0 also (in which case addPostRewrite()
272  // is not called).
273  if (getOptLevel() == CodeGenOpt::None)
274  addPass(createSystemZPostRewritePass(getSystemZTargetMachine()));
275 }
276 
277 void SystemZPassConfig::addPreSched2() {
278  if (getOptLevel() != CodeGenOpt::None)
279  addPass(&IfConverterID);
280 }
281 
282 void SystemZPassConfig::addPreEmitPass() {
283  // Do instruction shortening before compare elimination because some
284  // vector instructions will be shortened into opcodes that compare
285  // elimination recognizes.
286  if (getOptLevel() != CodeGenOpt::None)
287  addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false);
288 
289  // We eliminate comparisons here rather than earlier because some
290  // transformations can change the set of available CC values and we
291  // generally want those transformations to have priority. This is
292  // especially true in the commonest case where the result of the comparison
293  // is used by a single in-range branch instruction, since we will then
294  // be able to fuse the compare and the branch instead.
295  //
296  // For example, two-address NILF can sometimes be converted into
297  // three-address RISBLG. NILF produces a CC value that indicates whether
298  // the low word is zero, but RISBLG does not modify CC at all. On the
299  // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG.
300  // The CC value produced by NILL isn't useful for our purposes, but the
301  // value produced by RISBG can be used for any comparison with zero
302  // (not just equality). So there are some transformations that lose
303  // CC values (while still being worthwhile) and others that happen to make
304  // the CC result more useful than it was originally.
305  //
306  // Another reason is that we only want to use BRANCH ON COUNT in cases
307  // where we know that the count register is not going to be spilled.
308  //
309  // Doing it so late makes it more likely that a register will be reused
310  // between the comparison and the branch, but it isn't clear whether
311  // preventing that would be a win or not.
312  if (getOptLevel() != CodeGenOpt::None)
313  addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false);
314  addPass(createSystemZLongBranchPass(getSystemZTargetMachine()));
315 
316  // Do final scheduling after all other optimizations, to get an
317  // optimal input for the decoder (branch relaxation must happen
318  // after block placement).
319  if (getOptLevel() != CodeGenOpt::None)
320  addPass(&PostMachineSchedulerID);
321 }
322 
324  return new SystemZPassConfig(*this, PM);
325 }
326 
329  return TargetTransformInfo(SystemZTTIImpl(this, F));
330 }
llvm::createSystemZLongBranchPass
FunctionPass * createSystemZLongBranchPass(SystemZTargetMachine &TM)
Definition: SystemZLongBranch.cpp:469
llvm
---------------------— PointerInfo ------------------------------------—
Definition: AllocatorList.h:23
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:167
llvm::StringRef::empty
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:153
Optional.h
UsesVectorABI
static bool UsesVectorABI(StringRef CPU, StringRef FS)
Definition: SystemZTargetMachine.cpp:38
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
llvm::Function
Definition: Function.h:61
llvm::Attribute
Definition: Attributes.h:52
StringRef.h
llvm::createSystemZLDCleanupPass
FunctionPass * createSystemZLDCleanupPass(SystemZTargetMachine &TM)
Definition: SystemZLDCleanup.cpp:55
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::CodeModel::Medium
@ Medium
Definition: CodeGen.h:28
llvm::SmallVector
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1168
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::createSystemZISelDag
FunctionPass * createSystemZISelDag(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
Definition: SystemZISelDAGToDAG.cpp:382
llvm::createSystemZShortenInstPass
FunctionPass * createSystemZShortenInstPass(SystemZTargetMachine &TM)
Definition: SystemZShortenInst.cpp:59
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
getEffectiveSystemZCodeModel
static CodeModel::Model getEffectiveSystemZCodeModel(Optional< CodeModel::Model > CM, Reloc::Model RM, bool JIT)
Definition: SystemZTargetMachine.cpp:147
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::Optional< Reloc::Model >
SystemZMCTargetDesc.h
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::SystemZTargetMachine::~SystemZTargetMachine
~SystemZTargetMachine() override
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::CodeModel::Kernel
@ Kernel
Definition: CodeGen.h:28
SystemZTargetInfo.h
F
#define F(x, y, z)
Definition: MD5.cpp:56
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
llvm::getTheSystemZTarget
Target & getTheSystemZTarget()
Definition: SystemZTargetInfo.cpp:14
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:784
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
SystemZ.h
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:100
llvm::SystemZTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: SystemZTargetMachine.cpp:328
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:245
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:301
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:56
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:98
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: SystemZTargetMachine.cpp:100
SystemZTargetMachine.h
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::createSystemZElimComparePass
FunctionPass * createSystemZElimComparePass(SystemZTargetMachine &TM)
Definition: SystemZElimCompare.cpp:750
LLVMInitializeSystemZTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget()
Definition: SystemZTargetMachine.cpp:32
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:120
I
#define I(x, y, z)
Definition: MD5.cpp:59
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:850
llvm::SystemZTargetMachine
Definition: SystemZTargetMachine.h:27
TargetPassConfig.h
SystemZTargetTransformInfo.h
llvm::SystemZTargetMachine::getSubtargetImpl
const SystemZSubtarget * getSubtargetImpl() const =delete
llvm::SystemZSubtarget
Definition: SystemZSubtarget.h:33
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:266
llvm::SystemZTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: SystemZTargetMachine.cpp:323
llvm::SystemZTTIImpl
Definition: SystemZTargetTransformInfo.h:18
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:472
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
computeDataLayout
static std::string computeDataLayout(const Triple &TT, StringRef CPU, StringRef FS)
Definition: SystemZTargetMachine.cpp:65
llvm::createSystemZTDCPass
FunctionPass * createSystemZTDCPass()
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
llvm::SystemZTargetMachine::SystemZTargetMachine
SystemZTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: SystemZTargetMachine.cpp:161
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:393
CodeGen.h
SmallVector.h
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::createSystemZPostRewritePass
FunctionPass * createSystemZPostRewritePass(SystemZTargetMachine &TM)
llvm::PostMachineSchedulerID
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
Definition: MachineScheduler.cpp:241
llvm::createSystemZCopyPhysRegsPass
FunctionPass * createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM)
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:436
TargetRegistry.h
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:99
SystemZMachineScheduler.h
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:155
TargetLoweringObjectFileImpl.h