LLVM 19.0.0git
SPIRVTargetMachine.cpp
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1//===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about SPIR-V target spec.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SPIRVTargetMachine.h"
14#include "SPIRV.h"
15#include "SPIRVCallLowering.h"
16#include "SPIRVGlobalRegistry.h"
17#include "SPIRVLegalizerInfo.h"
25#include "llvm/CodeGen/Passes.h"
30#include "llvm/Pass.h"
33#include <optional>
34
35using namespace llvm;
36
38 // Register the target.
42
47}
48
49static std::string computeDataLayout(const Triple &TT) {
50 const auto Arch = TT.getArch();
51 // TODO: this probably needs to be revisited:
52 // Logical SPIR-V has no pointer size, so any fixed pointer size would be
53 // wrong. The choice to default to 32 or 64 is just motivated by another
54 // memory model used for graphics: PhysicalStorageBuffer64. But it shouldn't
55 // mean anything.
56 if (Arch == Triple::spirv32)
57 return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
58 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
59 return "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
60 "v96:128-v192:256-v256:256-v512:512-v1024:1024";
61}
62
63static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
64 if (!RM)
65 return Reloc::PIC_;
66 return *RM;
67}
68
69// Pin SPIRVTargetObjectFile's vtables to this file.
71
73 StringRef CPU, StringRef FS,
75 std::optional<Reloc::Model> RM,
76 std::optional<CodeModel::Model> CM,
77 CodeGenOptLevel OL, bool JIT)
78 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
80 getEffectiveCodeModel(CM, CodeModel::Small), OL),
81 TLOF(std::make_unique<SPIRVTargetObjectFile>()),
82 Subtarget(TT, CPU.str(), FS.str(), *this) {
84 setGlobalISel(true);
85 setFastISel(false);
86 setO0WantsFastISel(false);
88}
89
90namespace {
91// SPIR-V Code Generator Pass Configuration Options.
92class SPIRVPassConfig : public TargetPassConfig {
93public:
94 SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
95 : TargetPassConfig(TM, PM), TM(TM) {}
96
97 SPIRVTargetMachine &getSPIRVTargetMachine() const {
98 return getTM<SPIRVTargetMachine>();
99 }
100 void addIRPasses() override;
101 void addISelPrepare() override;
102
103 bool addIRTranslator() override;
104 void addPreLegalizeMachineIR() override;
105 bool addLegalizeMachineIR() override;
106 bool addRegBankSelect() override;
107 bool addGlobalInstructionSelect() override;
108
109 FunctionPass *createTargetRegisterAllocator(bool) override;
110 void addFastRegAlloc() override {}
111 void addOptimizedRegAlloc() override {}
112
113 void addPostRegAlloc() override;
114
115private:
116 const SPIRVTargetMachine &TM;
117};
118} // namespace
119
120// We do not use physical registers, and maintain virtual registers throughout
121// the entire pipeline, so return nullptr to disable register allocation.
122FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
123 return nullptr;
124}
125
126// Disable passes that break from assuming no virtual registers exist.
127void SPIRVPassConfig::addPostRegAlloc() {
128 // Do not work with vregs instead of physical regs.
129 disablePass(&MachineCopyPropagationID);
130 disablePass(&PostRAMachineSinkingID);
131 disablePass(&PostRASchedulerID);
132 disablePass(&FuncletLayoutID);
133 disablePass(&StackMapLivenessID);
134 disablePass(&PatchableFunctionID);
135 disablePass(&ShrinkWrapID);
136 disablePass(&LiveDebugValuesID);
137 disablePass(&MachineLateInstrsCleanupID);
138
139 // Do not work with OpPhi.
140 disablePass(&BranchFolderPassID);
141 disablePass(&MachineBlockPlacementID);
142
144}
145
148 return TargetTransformInfo(SPIRVTTIImpl(this, F));
149}
150
152 return new SPIRVPassConfig(*this, PM);
153}
154
155void SPIRVPassConfig::addIRPasses() {
156 if (TM.getSubtargetImpl()->isVulkanEnv()) {
157 // Once legalized, we need to structurize the CFG to follow the spec.
158 // This is done through the following 8 steps.
159 // TODO(#75801): add the remaining steps.
160
161 // 1. Simplify loop for subsequent transformations. After this steps, loops
162 // have the following properties:
163 // - loops have a single entry edge (pre-header to loop header).
164 // - all loop exits are dominated by the loop pre-header.
165 // - loops have a single back-edge.
166 addPass(createLoopSimplifyPass());
167 }
168
173}
174
175void SPIRVPassConfig::addISelPrepare() {
176 addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
178}
179
180bool SPIRVPassConfig::addIRTranslator() {
181 addPass(new IRTranslator(getOptLevel()));
182 return false;
183}
184
185void SPIRVPassConfig::addPreLegalizeMachineIR() {
187}
188
189// Use the default legalizer.
190bool SPIRVPassConfig::addLegalizeMachineIR() {
191 addPass(new Legalizer());
192 return false;
193}
194
195// Do not add the RegBankSelect pass, as we only ever need virtual registers.
196bool SPIRVPassConfig::addRegBankSelect() {
197 disablePass(&RegBankSelect::ID);
198 return false;
199}
200
201namespace {
202// A custom subclass of InstructionSelect, which is mostly the same except from
203// not requiring RegBankSelect to occur previously.
204class SPIRVInstructionSelect : public InstructionSelect {
205 // We don't use register banks, so unset the requirement for them
206 MachineFunctionProperties getRequiredProperties() const override {
208 MachineFunctionProperties::Property::RegBankSelected);
209 }
210};
211} // namespace
212
213// Add the custom SPIRVInstructionSelect from above.
214bool SPIRVPassConfig::addGlobalInstructionSelect() {
215 addPass(new SPIRVInstructionSelect());
216 return false;
217}
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const char LLVMTargetMachineRef TM
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget()
Target-Independent Code Generator Pass Configuration Options pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
This pass is responsible for selecting generic machine instructions to target-specific instructions.
MachineFunctionProperties getRequiredProperties() const override
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & reset(Property P)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
SPIRVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void setFastISel(bool Enable)
void setRequiresStructuredCFG(bool Value)
void setGlobalISel(bool Enable)
void setO0WantsFastISel(bool Enable)
Target-Independent Code Generator Pass Configuration Options.
virtual void addPostRegAlloc()
This method may be implemented by targets that want to run passes after register allocation pass pipe...
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addISelPrepare()
Add common passes that perform LLVM IR to IR transforms in preparation for instruction selection.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
Target & getTheSPIRV32Target()
FunctionPass * createSPIRVPreLegalizerPass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
FunctionPass * createSPIRVStripConvergenceIntrinsicsPass()
FunctionPass * createSPIRVEmitIntrinsicsPass(SPIRVTargetMachine *TM)
char & LiveDebugValuesID
LiveDebugValues pass.
void initializeSPIRVModuleAnalysisPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:286
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
Target & getTheSPIRV64Target()
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
Target & getTheSPIRVLogicalTarget()
FunctionPass * createSPIRVRegularizerPass()
void initializeSPIRVConvergenceRegionAnalysisWrapperPassPass(PassRegistry &)
char & MachineBlockPlacementID
MachineBlockPlacement - This pass places basic blocks based on branch probabilities.
char & BranchFolderPassID
BranchFolding - This pass performs machine code CFG based optimizations to delete branches to branche...
ModulePass * createSPIRVPrepareFunctionsPass(const SPIRVTargetMachine &TM)
Pass * createLoopSimplifyPass()
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
RegisterTargetMachine - Helper template for registering a target machine implementation,...