12 #ifndef LLVM_CODEGEN_REGALLOCGREEDY_H_
13 #define LLVM_CODEGEN_REGALLOCGREEDY_H_
44 class AllocationOrder;
47 class LiveDebugVariables;
50 class MachineBasicBlock;
51 class MachineBlockFrequencyInfo;
52 class MachineDominatorTree;
54 class MachineLoopInfo;
55 class MachineOptimizationRemarkEmitter;
56 class MachineOptimizationRemarkMissed;
59 class TargetInstrInfo;
81 unsigned NextCascade = 1;
90 return getStage(VirtReg.
reg());
99 setStage(VirtReg.
reg(), Stage);
106 return getStage(
Reg);
117 unsigned Cascade = getCascade(
Reg);
119 Cascade = NextCascade++;
120 setCascade(
Reg, Cascade);
126 unsigned Cascade = getCascade(
Reg);
128 Cascade = NextCascade;
132 template <
typename Iterator>
134 for (; Begin != End; ++Begin) {
154 using PQueue = std::priority_queue<std::pair<unsigned, unsigned>>;
159 using RecoloringStack =
180 std::unique_ptr<Spiller> SpillerInstance;
182 std::unique_ptr<VirtRegAuxInfo> VRAI;
184 std::unique_ptr<RegAllocEvictionAdvisor> EvictAdvisor;
203 static const char *
const StageName[];
207 std::unique_ptr<SplitAnalysis> SA;
208 std::unique_ptr<SplitEditor> SE;
211 InterferenceCache IntfCache;
214 SmallVector<SpillPlacement::BlockConstraint, 8> SplitConstraints;
217 struct GlobalSplitCandidate {
225 InterferenceCache::Cursor Intf;
228 BitVector LiveBundles;
229 SmallVector<unsigned, 8> ActiveBlocks;
231 void reset(InterferenceCache &Cache, MCRegister
Reg) {
234 Intf.setPhysReg(Cache,
Reg);
236 ActiveBlocks.clear();
240 unsigned getBundles(SmallVectorImpl<unsigned> &
B,
unsigned C) {
242 for (
unsigned I : LiveBundles.set_bits())
254 SmallVector<GlobalSplitCandidate, 32> GlobalCand;
256 enum :
unsigned {
NoCand = ~0u };
260 SmallVector<unsigned, 32> BundleCand;
263 BlockFrequency CSRCost;
266 SmallSetVector<const LiveInterval *, 8> SetOfBrokenHints;
270 ArrayRef<uint8_t> RegCosts;
274 bool RegClassPriorityTrumpsGlobalness;
284 void releaseMemory()
override;
290 void aboutToRemoveInterval(
const LiveInterval &)
override;
312 bool LRE_CanEraseVirtReg(
Register)
override;
313 void LRE_WillShrinkVirtReg(
Register)
override;
318 bool hasVirtRegAlloc();
322 bool growRegion(GlobalSplitCandidate &Cand);
325 bool calcCompactRegion(GlobalSplitCandidate &);
330 bool mayRecolorAllInterferences(
MCRegister PhysReg,
343 unsigned calculateRegionSplitCost(
const LiveInterval &VirtReg,
346 unsigned &NumCands,
bool IgnoreCSR);
348 unsigned doRegionSplit(
const LiveInterval &VirtReg,
unsigned BestCand,
354 uint8_t &CostPerUseLimit,
356 void initializeCSRCost();
372 void tryHintsRecoloring();
385 : Freq(Freq),
Reg(
Reg), PhysReg(PhysReg) {}
387 using HintsInfo = SmallVector<HintInfo, 4>;
389 BlockFrequency getBrokenHintFreq(
const HintsInfo &, MCRegister);
390 void collectHintInfo(Register, HintsInfo &);
393 struct RAGreedyStats {
394 unsigned Reloads = 0;
395 unsigned FoldedReloads = 0;
396 unsigned ZeroCostFoldedReloads = 0;
398 unsigned FoldedSpills = 0;
400 float ReloadsCost = 0.0f;
401 float FoldedReloadsCost = 0.0f;
402 float SpillsCost = 0.0f;
403 float FoldedSpillsCost = 0.0f;
404 float CopiesCost = 0.0f;
407 return !(Reloads || FoldedReloads || Spills || FoldedSpills ||
408 ZeroCostFoldedReloads ||
Copies);
411 void add(RAGreedyStats other) {
412 Reloads += other.Reloads;
413 FoldedReloads += other.FoldedReloads;
414 ZeroCostFoldedReloads += other.ZeroCostFoldedReloads;
415 Spills += other.Spills;
416 FoldedSpills += other.FoldedSpills;
418 ReloadsCost += other.ReloadsCost;
419 FoldedReloadsCost += other.FoldedReloadsCost;
420 SpillsCost += other.SpillsCost;
421 FoldedSpillsCost += other.FoldedSpillsCost;
422 CopiesCost += other.CopiesCost;
425 void report(MachineOptimizationRemarkMissed &R);
429 RAGreedyStats computeStats(MachineBasicBlock &
MBB);
432 RAGreedyStats reportStats(MachineLoop *L);
438 #endif // #ifndef LLVM_CODEGEN_REGALLOCGREEDY_H_