LLVM  14.0.0git
X86FixupBWInsts.cpp
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1 //===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file defines the pass that looks through the machine instructions
10 /// late in the compilation, and finds byte or word instructions that
11 /// can be profitably replaced with 32 bit instructions that give equivalent
12 /// results for the bits of the results that are used. There are two possible
13 /// reasons to do this.
14 ///
15 /// One reason is to avoid false-dependences on the upper portions
16 /// of the registers. Only instructions that have a destination register
17 /// which is not in any of the source registers can be affected by this.
18 /// Any instruction where one of the source registers is also the destination
19 /// register is unaffected, because it has a true dependence on the source
20 /// register already. So, this consideration primarily affects load
21 /// instructions and register-to-register moves. It would
22 /// seem like cmov(s) would also be affected, but because of the way cmov is
23 /// really implemented by most machines as reading both the destination and
24 /// and source registers, and then "merging" the two based on a condition,
25 /// it really already should be considered as having a true dependence on the
26 /// destination register as well.
27 ///
28 /// The other reason to do this is for potential code size savings. Word
29 /// operations need an extra override byte compared to their 32 bit
30 /// versions. So this can convert many word operations to their larger
31 /// size, saving a byte in encoding. This could introduce partial register
32 /// dependences where none existed however. As an example take:
33 /// orw ax, $0x1000
34 /// addw ax, $3
35 /// now if this were to get transformed into
36 /// orw ax, $1000
37 /// addl eax, $3
38 /// because the addl encodes shorter than the addw, this would introduce
39 /// a use of a register that was only partially written earlier. On older
40 /// Intel processors this can be quite a performance penalty, so this should
41 /// probably only be done when it can be proven that a new partial dependence
42 /// wouldn't be created, or when your know a newer processor is being
43 /// targeted, or when optimizing for minimum code size.
44 ///
45 //===----------------------------------------------------------------------===//
46 
47 #include "X86.h"
48 #include "X86InstrInfo.h"
49 #include "X86Subtarget.h"
50 #include "llvm/ADT/Statistic.h"
59 #include "llvm/CodeGen/Passes.h"
61 #include "llvm/Support/Debug.h"
63 using namespace llvm;
64 
65 #define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
66 #define FIXUPBW_NAME "x86-fixup-bw-insts"
67 
68 #define DEBUG_TYPE FIXUPBW_NAME
69 
70 // Option to allow this optimization pass to have fine-grained control.
71 static cl::opt<bool>
72  FixupBWInsts("fixup-byte-word-insts",
73  cl::desc("Change byte and word instructions to larger sizes"),
74  cl::init(true), cl::Hidden);
75 
76 namespace {
77 class FixupBWInstPass : public MachineFunctionPass {
78  /// Loop over all of the instructions in the basic block replacing applicable
79  /// byte or word instructions with better alternatives.
80  void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
81 
82  /// This sets the \p SuperDestReg to the 32 bit super reg of the original
83  /// destination register of the MachineInstr passed in. It returns true if
84  /// that super register is dead just prior to \p OrigMI, and false if not.
85  bool getSuperRegDestIfDead(MachineInstr *OrigMI,
86  Register &SuperDestReg) const;
87 
88  /// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
89  /// register if it is safe to do so. Return the replacement instruction if
90  /// OK, otherwise return nullptr.
91  MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
92 
93  /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
94  /// safe to do so. Return the replacement instruction if OK, otherwise return
95  /// nullptr.
96  MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
97 
98  /// Change the MachineInstr \p MI into the equivalent extend to 32 bit
99  /// register if it is safe to do so. Return the replacement instruction if
100  /// OK, otherwise return nullptr.
101  MachineInstr *tryReplaceExtend(unsigned New32BitOpcode,
102  MachineInstr *MI) const;
103 
104  // Change the MachineInstr \p MI into an eqivalent 32 bit instruction if
105  // possible. Return the replacement instruction if OK, return nullptr
106  // otherwise.
107  MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB) const;
108 
109 public:
110  static char ID;
111 
112  StringRef getPassName() const override { return FIXUPBW_DESC; }
113 
114  FixupBWInstPass() : MachineFunctionPass(ID) { }
115 
116  void getAnalysisUsage(AnalysisUsage &AU) const override {
117  AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
118  // guide some heuristics.
122  }
123 
124  /// Loop over all of the basic blocks, replacing byte and word instructions by
125  /// equivalent 32 bit instructions where performance or code size can be
126  /// improved.
127  bool runOnMachineFunction(MachineFunction &MF) override;
128 
129  MachineFunctionProperties getRequiredProperties() const override {
132  }
133 
134 private:
135  MachineFunction *MF = nullptr;
136 
137  /// Machine instruction info used throughout the class.
138  const X86InstrInfo *TII = nullptr;
139 
140  const TargetRegisterInfo *TRI = nullptr;
141 
142  /// Local member for function's OptForSize attribute.
143  bool OptForSize = false;
144 
145  /// Machine loop info used for guiding some heruistics.
146  MachineLoopInfo *MLI = nullptr;
147 
148  /// Register Liveness information after the current instruction.
149  LivePhysRegs LiveRegs;
150 
151  ProfileSummaryInfo *PSI;
153 };
154 char FixupBWInstPass::ID = 0;
155 }
156 
157 INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
158 
159 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
160 
161 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
162  if (!FixupBWInsts || skipFunction(MF.getFunction()))
163  return false;
164 
165  this->MF = &MF;
166  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
168  MLI = &getAnalysis<MachineLoopInfo>();
169  PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
170  MBFI = (PSI && PSI->hasProfileSummary()) ?
171  &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
172  nullptr;
173  LiveRegs.init(TII->getRegisterInfo());
174 
175  LLVM_DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
176 
177  // Process all basic blocks.
178  for (auto &MBB : MF)
179  processBasicBlock(MF, MBB);
180 
181  LLVM_DEBUG(dbgs() << "End X86FixupBWInsts\n";);
182 
183  return true;
184 }
185 
186 /// Check if after \p OrigMI the only portion of super register
187 /// of the destination register of \p OrigMI that is alive is that
188 /// destination register.
189 ///
190 /// If so, return that super register in \p SuperDestReg.
191 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
192  Register &SuperDestReg) const {
193  const X86RegisterInfo *TRI = &TII->getRegisterInfo();
194  Register OrigDestReg = OrigMI->getOperand(0).getReg();
195  SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
196 
197  const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
198 
199  // Make sure that the sub-register that this instruction has as its
200  // destination is the lowest order sub-register of the super-register.
201  // If it isn't, then the register isn't really dead even if the
202  // super-register is considered dead.
203  if (SubRegIdx == X86::sub_8bit_hi)
204  return false;
205 
206  // If neither the destination-super register nor any applicable subregisters
207  // are live after this instruction, then the super register is safe to use.
208  if (!LiveRegs.contains(SuperDestReg)) {
209  // If the original destination register was not the low 8-bit subregister
210  // then the super register check is sufficient.
211  if (SubRegIdx != X86::sub_8bit)
212  return true;
213  // If the original destination register was the low 8-bit subregister and
214  // we also need to check the 16-bit subregister and the high 8-bit
215  // subregister.
216  if (!LiveRegs.contains(getX86SubSuperRegister(OrigDestReg, 16)) &&
217  !LiveRegs.contains(getX86SubSuperRegister(SuperDestReg, 8,
218  /*High=*/true)))
219  return true;
220  // Otherwise, we have a little more checking to do.
221  }
222 
223  // If we get here, the super-register destination (or some part of it) is
224  // marked as live after the original instruction.
225  //
226  // The X86 backend does not have subregister liveness tracking enabled,
227  // so liveness information might be overly conservative. Specifically, the
228  // super register might be marked as live because it is implicitly defined
229  // by the instruction we are examining.
230  //
231  // However, for some specific instructions (this pass only cares about MOVs)
232  // we can produce more precise results by analysing that MOV's operands.
233  //
234  // Indeed, if super-register is not live before the mov it means that it
235  // was originally <read-undef> and so we are free to modify these
236  // undef upper bits. That may happen in case where the use is in another MBB
237  // and the vreg/physreg corresponding to the move has higher width than
238  // necessary (e.g. due to register coalescing with a "truncate" copy).
239  // So, we would like to handle patterns like this:
240  //
241  // %bb.2: derived from LLVM BB %if.then
242  // Live Ins: %rdi
243  // Predecessors according to CFG: %bb.0
244  // %ax<def> = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax
245  // ; No implicit %eax
246  // Successors according to CFG: %bb.3(?%)
247  //
248  // %bb.3: derived from LLVM BB %if.end
249  // Live Ins: %eax Only %ax is actually live
250  // Predecessors according to CFG: %bb.2 %bb.1
251  // %ax = KILL %ax, implicit killed %eax
252  // RET 0, %ax
253  unsigned Opc = OrigMI->getOpcode(); (void)Opc;
254  // These are the opcodes currently known to work with the code below, if
255  // something // else will be added we need to ensure that new opcode has the
256  // same properties.
257  if (Opc != X86::MOV8rm && Opc != X86::MOV16rm && Opc != X86::MOV8rr &&
258  Opc != X86::MOV16rr)
259  return false;
260 
261  bool IsDefined = false;
262  for (auto &MO: OrigMI->implicit_operands()) {
263  if (!MO.isReg())
264  continue;
265 
266  assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
267 
268  if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
269  IsDefined = true;
270 
271  // If MO is a use of any part of the destination register but is not equal
272  // to OrigDestReg or one of its subregisters, we cannot use SuperDestReg.
273  // For example, if OrigDestReg is %al then an implicit use of %ah, %ax,
274  // %eax, or %rax will prevent us from using the %eax register.
275  if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
276  TRI->regsOverlap(SuperDestReg, MO.getReg()))
277  return false;
278  }
279  // Reg is not Imp-def'ed -> it's live both before/after the instruction.
280  if (!IsDefined)
281  return false;
282 
283  // Otherwise, the Reg is not live before the MI and the MOV can't
284  // make it really live, so it's in fact dead even after the MI.
285  return true;
286 }
287 
288 MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
289  MachineInstr *MI) const {
290  Register NewDestReg;
291 
292  // We are going to try to rewrite this load to a larger zero-extending
293  // load. This is safe if all portions of the 32 bit super-register
294  // of the original destination register, except for the original destination
295  // register are dead. getSuperRegDestIfDead checks that.
296  if (!getSuperRegDestIfDead(MI, NewDestReg))
297  return nullptr;
298 
299  // Safe to change the instruction.
300  MachineInstrBuilder MIB =
301  BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
302 
303  unsigned NumArgs = MI->getNumOperands();
304  for (unsigned i = 1; i < NumArgs; ++i)
305  MIB.add(MI->getOperand(i));
306 
307  MIB.setMemRefs(MI->memoperands());
308 
309  // If it was debug tracked, record a substitution.
310  if (unsigned OldInstrNum = MI->peekDebugInstrNum()) {
311  unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(),
312  MI->getOperand(0).getReg());
313  unsigned NewInstrNum = MIB->getDebugInstrNum(*MF);
314  MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
315  }
316 
317  return MIB;
318 }
319 
320 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
321  assert(MI->getNumExplicitOperands() == 2);
322  auto &OldDest = MI->getOperand(0);
323  auto &OldSrc = MI->getOperand(1);
324 
325  Register NewDestReg;
326  if (!getSuperRegDestIfDead(MI, NewDestReg))
327  return nullptr;
328 
329  Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
330 
331  // This is only correct if we access the same subregister index: otherwise,
332  // we could try to replace "movb %ah, %al" with "movl %eax, %eax".
333  const X86RegisterInfo *TRI = &TII->getRegisterInfo();
334  if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
335  TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
336  return nullptr;
337 
338  // Safe to change the instruction.
339  // Don't set src flags, as we don't know if we're also killing the superreg.
340  // However, the superregister might not be defined; make it explicit that
341  // we don't care about the higher bits by reading it as Undef, and adding
342  // an imp-use on the original subregister.
343  MachineInstrBuilder MIB =
344  BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
345  .addReg(NewSrcReg, RegState::Undef)
346  .addReg(OldSrc.getReg(), RegState::Implicit);
347 
348  // Drop imp-defs/uses that would be redundant with the new def/use.
349  for (auto &Op : MI->implicit_operands())
350  if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
351  MIB.add(Op);
352 
353  return MIB;
354 }
355 
356 MachineInstr *FixupBWInstPass::tryReplaceExtend(unsigned New32BitOpcode,
357  MachineInstr *MI) const {
358  Register NewDestReg;
359  if (!getSuperRegDestIfDead(MI, NewDestReg))
360  return nullptr;
361 
362  // Don't interfere with formation of CBW instructions which should be a
363  // shorter encoding than even the MOVSX32rr8. It's also immune to partial
364  // merge issues on Intel CPUs.
365  if (MI->getOpcode() == X86::MOVSX16rr8 &&
366  MI->getOperand(0).getReg() == X86::AX &&
367  MI->getOperand(1).getReg() == X86::AL)
368  return nullptr;
369 
370  // Safe to change the instruction.
371  MachineInstrBuilder MIB =
372  BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
373 
374  unsigned NumArgs = MI->getNumOperands();
375  for (unsigned i = 1; i < NumArgs; ++i)
376  MIB.add(MI->getOperand(i));
377 
378  MIB.setMemRefs(MI->memoperands());
379 
380  if (unsigned OldInstrNum = MI->peekDebugInstrNum()) {
381  unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(),
382  MI->getOperand(0).getReg());
383  unsigned NewInstrNum = MIB->getDebugInstrNum(*MF);
384  MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
385  }
386 
387  return MIB;
388 }
389 
390 MachineInstr *FixupBWInstPass::tryReplaceInstr(MachineInstr *MI,
391  MachineBasicBlock &MBB) const {
392  // See if this is an instruction of the type we are currently looking for.
393  switch (MI->getOpcode()) {
394 
395  case X86::MOV8rm:
396  // Only replace 8 bit loads with the zero extending versions if
397  // in an inner most loop and not optimizing for size. This takes
398  // an extra byte to encode, and provides limited performance upside.
399  if (MachineLoop *ML = MLI->getLoopFor(&MBB))
400  if (ML->begin() == ML->end() && !OptForSize)
401  return tryReplaceLoad(X86::MOVZX32rm8, MI);
402  break;
403 
404  case X86::MOV16rm:
405  // Always try to replace 16 bit load with 32 bit zero extending.
406  // Code size is the same, and there is sometimes a perf advantage
407  // from eliminating a false dependence on the upper portion of
408  // the register.
409  return tryReplaceLoad(X86::MOVZX32rm16, MI);
410 
411  case X86::MOV8rr:
412  case X86::MOV16rr:
413  // Always try to replace 8/16 bit copies with a 32 bit copy.
414  // Code size is either less (16) or equal (8), and there is sometimes a
415  // perf advantage from eliminating a false dependence on the upper portion
416  // of the register.
417  return tryReplaceCopy(MI);
418 
419  case X86::MOVSX16rr8:
420  return tryReplaceExtend(X86::MOVSX32rr8, MI);
421  case X86::MOVSX16rm8:
422  return tryReplaceExtend(X86::MOVSX32rm8, MI);
423  case X86::MOVZX16rr8:
424  return tryReplaceExtend(X86::MOVZX32rr8, MI);
425  case X86::MOVZX16rm8:
426  return tryReplaceExtend(X86::MOVZX32rm8, MI);
427 
428  default:
429  // nothing to do here.
430  break;
431  }
432 
433  return nullptr;
434 }
435 
436 void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
438 
439  // This algorithm doesn't delete the instructions it is replacing
440  // right away. By leaving the existing instructions in place, the
441  // register liveness information doesn't change, and this makes the
442  // analysis that goes on be better than if the replaced instructions
443  // were immediately removed.
444  //
445  // This algorithm always creates a replacement instruction
446  // and notes that and the original in a data structure, until the
447  // whole BB has been analyzed. This keeps the replacement instructions
448  // from making it seem as if the larger register might be live.
450 
451  // Start computing liveness for this block. We iterate from the end to be able
452  // to update this for each instruction.
453  LiveRegs.clear();
454  // We run after PEI, so we need to AddPristinesAndCSRs.
455  LiveRegs.addLiveOuts(MBB);
456 
457  OptForSize = MF.getFunction().hasOptSize() ||
458  llvm::shouldOptimizeForSize(&MBB, PSI, MBFI);
459 
460  for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
461  MachineInstr *MI = &*I;
462 
463  if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
464  MIReplacements.push_back(std::make_pair(MI, NewMI));
465 
466  // We're done with this instruction, update liveness for the next one.
467  LiveRegs.stepBackward(*MI);
468  }
469 
470  while (!MIReplacements.empty()) {
471  MachineInstr *MI = MIReplacements.back().first;
472  MachineInstr *NewMI = MIReplacements.back().second;
473  MIReplacements.pop_back();
474  MBB.insert(MI, NewMI);
475  MBB.erase(MI);
476  }
477 }
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Definition: README.txt:29
llvm::MachineInstr::getDebugInstrNum
unsigned getDebugInstrNum()
Fetch the instruction number of this MachineInstr.
Definition: MachineInstr.cpp:2373
MI
IRTranslator LLVM IR MI
Definition: IRTranslator.cpp:105
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@ AL
Definition: AArch64BaseInfo.h:269
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const MachineInstrBuilder & add(const MachineOperand &MO) const
Definition: MachineInstrBuilder.h:224
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Definition: SmallVector.h:1168
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Definition: X86Subtarget.h:52
FixupBWInsts
static cl::opt< bool > FixupBWInsts("fixup-byte-word-insts", cl::desc("Change byte and word instructions to larger sizes"), cl::init(true), cl::Hidden)
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const TargetRegisterInfo * getTargetRegisterInfo() const
Definition: MachineRegisterInfo.h:153
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Definition: MachineFunctionPass.h:30
MachineSizeOpts.h
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A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
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@ Hidden
Definition: CommandLine.h:143
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Definition: TargetRegisterInfo.h:233
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Properties which a MachineFunction may have at a given point in time.
Definition: MachineFunction.h:111
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@ Undef
Value of the register doesn't matter.
Definition: MachineInstrBuilder.h:52
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unsigned const TargetRegisterInfo * TRI
Definition: MachineSink.cpp:1559
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void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Definition: MachineFunctionPass.cpp:102
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#define LLVM_DEBUG(X)
Definition: Debug.h:101
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Definition: MachineLoopInfo.h:90
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instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
Definition: MachineBasicBlock.cpp:1301
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getRegInfo - Return information about the registers currently in use.
Definition: MachineFunction.h:644
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Returns true if machine function MF is suggested to be size-optimized based on the profile.
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Definition: MachineBlockFrequencyInfo.h:33
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const MachineOperand & getOperand(unsigned i) const
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#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
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Definition: PassAnalysisSupport.h:47
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#define FIXUPBW_NAME
Definition: X86FixupBWInsts.cpp:66
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For a given register pair, return the sub-register index if the second register is a sub-register of ...
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Definition: X86FixupBWInsts.cpp:65
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Returns true if the two registers are equal or alias each other.
Definition: TargetRegisterInfo.h:418
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bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a sub-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:568
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Definition: MachineBasicBlock.h:95
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Definition: ProfileSummaryInfo.h:39
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const TargetSubtargetInfo & getSubtarget() const
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Definition: X86MCTargetDesc.cpp:813
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MachineFunctionPass.h
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::MachineInstrBuilder::addReg
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Definition: MachineInstrBuilder.h:97
llvm::MachineOperand::getReg
Register getReg() const
getReg - Returns the register number.
Definition: MachineOperand.h:360
llvm::LazyMachineBlockFrequencyInfoPass
This is an alternative analysis pass to MachineBlockFrequencyInfo.
Definition: LazyMachineBlockFrequencyInfo.h:37
llvm::createX86FixupBWInsts
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Definition: X86FixupBWInsts.cpp:159
llvm::MachineFunction
Definition: MachineFunction.h:234
llvm::X86InstrInfo
Definition: X86InstrInfo.h:130
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
llvm::MachineBasicBlock::rbegin
reverse_iterator rbegin()
Definition: MachineBasicBlock.h:272
llvm::MachineInstr::getOpcode
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:489
llvm::Register
Wrapper class representing virtual and physical registers.
Definition: Register.h:19
llvm::Function::hasOptSize
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:661
MBB
MachineBasicBlock & MBB
Definition: AArch64SLSHardening.cpp:74
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:600
llvm::MCRegisterInfo::isSuperRegisterEq
bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const
Returns true if RegB is a super-register of RegA or if RegB == RegA.
Definition: MCRegisterInfo.h:574
llvm::RegState::Implicit
@ Implicit
Not emitted register (e.g. carry, or temporary result).
Definition: MachineInstrBuilder.h:46
llvm::AMDGPU::SendMsg::Op
Op
Definition: SIDefines.h:325
llvm::MachineBasicBlock::insert
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
Definition: MachineBasicBlock.cpp:1314
llvm::MachineInstrBuilder::setMemRefs
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
Definition: MachineInstrBuilder.h:208
llvm::SmallVectorImpl::clear
void clear()
Definition: SmallVector.h:585
MachineInstrBuilder.h
llvm::BuildMI
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
Definition: MachineInstrBuilder.h:328
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::AnalysisUsage::addRequired
AnalysisUsage & addRequired()
Definition: PassAnalysisSupport.h:75
llvm::cl::desc
Definition: CommandLine.h:412
raw_ostream.h
X86InstrInfo.h
Debug.h
llvm::X86RegisterInfo
Definition: X86RegisterInfo.h:24
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38
LivePhysRegs.h