LLVM  12.0.0git
X86FixupBWInsts.cpp
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1 //===-- X86FixupBWInsts.cpp - Fixup Byte or Word instructions -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file defines the pass that looks through the machine instructions
10 /// late in the compilation, and finds byte or word instructions that
11 /// can be profitably replaced with 32 bit instructions that give equivalent
12 /// results for the bits of the results that are used. There are two possible
13 /// reasons to do this.
14 ///
15 /// One reason is to avoid false-dependences on the upper portions
16 /// of the registers. Only instructions that have a destination register
17 /// which is not in any of the source registers can be affected by this.
18 /// Any instruction where one of the source registers is also the destination
19 /// register is unaffected, because it has a true dependence on the source
20 /// register already. So, this consideration primarily affects load
21 /// instructions and register-to-register moves. It would
22 /// seem like cmov(s) would also be affected, but because of the way cmov is
23 /// really implemented by most machines as reading both the destination and
24 /// and source registers, and then "merging" the two based on a condition,
25 /// it really already should be considered as having a true dependence on the
26 /// destination register as well.
27 ///
28 /// The other reason to do this is for potential code size savings. Word
29 /// operations need an extra override byte compared to their 32 bit
30 /// versions. So this can convert many word operations to their larger
31 /// size, saving a byte in encoding. This could introduce partial register
32 /// dependences where none existed however. As an example take:
33 /// orw ax, $0x1000
34 /// addw ax, $3
35 /// now if this were to get transformed into
36 /// orw ax, $1000
37 /// addl eax, $3
38 /// because the addl encodes shorter than the addw, this would introduce
39 /// a use of a register that was only partially written earlier. On older
40 /// Intel processors this can be quite a performance penalty, so this should
41 /// probably only be done when it can be proven that a new partial dependence
42 /// wouldn't be created, or when your know a newer processor is being
43 /// targeted, or when optimizing for minimum code size.
44 ///
45 //===----------------------------------------------------------------------===//
46 
47 #include "X86.h"
48 #include "X86InstrInfo.h"
49 #include "X86Subtarget.h"
50 #include "llvm/ADT/Statistic.h"
59 #include "llvm/CodeGen/Passes.h"
61 #include "llvm/Support/Debug.h"
63 using namespace llvm;
64 
65 #define FIXUPBW_DESC "X86 Byte/Word Instruction Fixup"
66 #define FIXUPBW_NAME "x86-fixup-bw-insts"
67 
68 #define DEBUG_TYPE FIXUPBW_NAME
69 
70 // Option to allow this optimization pass to have fine-grained control.
71 static cl::opt<bool>
72  FixupBWInsts("fixup-byte-word-insts",
73  cl::desc("Change byte and word instructions to larger sizes"),
74  cl::init(true), cl::Hidden);
75 
76 namespace {
77 class FixupBWInstPass : public MachineFunctionPass {
78  /// Loop over all of the instructions in the basic block replacing applicable
79  /// byte or word instructions with better alternatives.
80  void processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
81 
82  /// This sets the \p SuperDestReg to the 32 bit super reg of the original
83  /// destination register of the MachineInstr passed in. It returns true if
84  /// that super register is dead just prior to \p OrigMI, and false if not.
85  bool getSuperRegDestIfDead(MachineInstr *OrigMI,
86  Register &SuperDestReg) const;
87 
88  /// Change the MachineInstr \p MI into the equivalent extending load to 32 bit
89  /// register if it is safe to do so. Return the replacement instruction if
90  /// OK, otherwise return nullptr.
91  MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
92 
93  /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
94  /// safe to do so. Return the replacement instruction if OK, otherwise return
95  /// nullptr.
96  MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
97 
98  /// Change the MachineInstr \p MI into the equivalent extend to 32 bit
99  /// register if it is safe to do so. Return the replacement instruction if
100  /// OK, otherwise return nullptr.
101  MachineInstr *tryReplaceExtend(unsigned New32BitOpcode,
102  MachineInstr *MI) const;
103 
104  // Change the MachineInstr \p MI into an eqivalent 32 bit instruction if
105  // possible. Return the replacement instruction if OK, return nullptr
106  // otherwise.
107  MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB) const;
108 
109 public:
110  static char ID;
111 
112  StringRef getPassName() const override { return FIXUPBW_DESC; }
113 
114  FixupBWInstPass() : MachineFunctionPass(ID) { }
115 
116  void getAnalysisUsage(AnalysisUsage &AU) const override {
117  AU.addRequired<MachineLoopInfo>(); // Machine loop info is used to
118  // guide some heuristics.
122  }
123 
124  /// Loop over all of the basic blocks, replacing byte and word instructions by
125  /// equivalent 32 bit instructions where performance or code size can be
126  /// improved.
127  bool runOnMachineFunction(MachineFunction &MF) override;
128 
129  MachineFunctionProperties getRequiredProperties() const override {
132  }
133 
134 private:
135  MachineFunction *MF = nullptr;
136 
137  /// Machine instruction info used throughout the class.
138  const X86InstrInfo *TII = nullptr;
139 
140  /// Local member for function's OptForSize attribute.
141  bool OptForSize = false;
142 
143  /// Machine loop info used for guiding some heruistics.
144  MachineLoopInfo *MLI = nullptr;
145 
146  /// Register Liveness information after the current instruction.
147  LivePhysRegs LiveRegs;
148 
149  ProfileSummaryInfo *PSI;
151 };
152 char FixupBWInstPass::ID = 0;
153 }
154 
155 INITIALIZE_PASS(FixupBWInstPass, FIXUPBW_NAME, FIXUPBW_DESC, false, false)
156 
157 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
158 
159 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
160  if (!FixupBWInsts || skipFunction(MF.getFunction()))
161  return false;
162 
163  this->MF = &MF;
164  TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
165  MLI = &getAnalysis<MachineLoopInfo>();
166  PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
167  MBFI = (PSI && PSI->hasProfileSummary()) ?
168  &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
169  nullptr;
170  LiveRegs.init(TII->getRegisterInfo());
171 
172  LLVM_DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
173 
174  // Process all basic blocks.
175  for (auto &MBB : MF)
176  processBasicBlock(MF, MBB);
177 
178  LLVM_DEBUG(dbgs() << "End X86FixupBWInsts\n";);
179 
180  return true;
181 }
182 
183 /// Check if after \p OrigMI the only portion of super register
184 /// of the destination register of \p OrigMI that is alive is that
185 /// destination register.
186 ///
187 /// If so, return that super register in \p SuperDestReg.
188 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI,
189  Register &SuperDestReg) const {
190  auto *TRI = &TII->getRegisterInfo();
191 
192  Register OrigDestReg = OrigMI->getOperand(0).getReg();
193  SuperDestReg = getX86SubSuperRegister(OrigDestReg, 32);
194 
195  const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg);
196 
197  // Make sure that the sub-register that this instruction has as its
198  // destination is the lowest order sub-register of the super-register.
199  // If it isn't, then the register isn't really dead even if the
200  // super-register is considered dead.
201  if (SubRegIdx == X86::sub_8bit_hi)
202  return false;
203 
204  // If neither the destination-super register nor any applicable subregisters
205  // are live after this instruction, then the super register is safe to use.
206  if (!LiveRegs.contains(SuperDestReg)) {
207  // If the original destination register was not the low 8-bit subregister
208  // then the super register check is sufficient.
209  if (SubRegIdx != X86::sub_8bit)
210  return true;
211  // If the original destination register was the low 8-bit subregister and
212  // we also need to check the 16-bit subregister and the high 8-bit
213  // subregister.
214  if (!LiveRegs.contains(getX86SubSuperRegister(OrigDestReg, 16)) &&
215  !LiveRegs.contains(getX86SubSuperRegister(SuperDestReg, 8,
216  /*High=*/true)))
217  return true;
218  // Otherwise, we have a little more checking to do.
219  }
220 
221  // If we get here, the super-register destination (or some part of it) is
222  // marked as live after the original instruction.
223  //
224  // The X86 backend does not have subregister liveness tracking enabled,
225  // so liveness information might be overly conservative. Specifically, the
226  // super register might be marked as live because it is implicitly defined
227  // by the instruction we are examining.
228  //
229  // However, for some specific instructions (this pass only cares about MOVs)
230  // we can produce more precise results by analysing that MOV's operands.
231  //
232  // Indeed, if super-register is not live before the mov it means that it
233  // was originally <read-undef> and so we are free to modify these
234  // undef upper bits. That may happen in case where the use is in another MBB
235  // and the vreg/physreg corresponding to the move has higher width than
236  // necessary (e.g. due to register coalescing with a "truncate" copy).
237  // So, we would like to handle patterns like this:
238  //
239  // %bb.2: derived from LLVM BB %if.then
240  // Live Ins: %rdi
241  // Predecessors according to CFG: %bb.0
242  // %ax<def> = MOV16rm killed %rdi, 1, %noreg, 0, %noreg, implicit-def %eax
243  // ; No implicit %eax
244  // Successors according to CFG: %bb.3(?%)
245  //
246  // %bb.3: derived from LLVM BB %if.end
247  // Live Ins: %eax Only %ax is actually live
248  // Predecessors according to CFG: %bb.2 %bb.1
249  // %ax = KILL %ax, implicit killed %eax
250  // RET 0, %ax
251  unsigned Opc = OrigMI->getOpcode(); (void)Opc;
252  // These are the opcodes currently known to work with the code below, if
253  // something // else will be added we need to ensure that new opcode has the
254  // same properties.
255  if (Opc != X86::MOV8rm && Opc != X86::MOV16rm && Opc != X86::MOV8rr &&
256  Opc != X86::MOV16rr)
257  return false;
258 
259  bool IsDefined = false;
260  for (auto &MO: OrigMI->implicit_operands()) {
261  if (!MO.isReg())
262  continue;
263 
264  assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
265 
266  if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
267  IsDefined = true;
268 
269  // If MO is a use of any part of the destination register but is not equal
270  // to OrigDestReg or one of its subregisters, we cannot use SuperDestReg.
271  // For example, if OrigDestReg is %al then an implicit use of %ah, %ax,
272  // %eax, or %rax will prevent us from using the %eax register.
273  if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
274  TRI->regsOverlap(SuperDestReg, MO.getReg()))
275  return false;
276  }
277  // Reg is not Imp-def'ed -> it's live both before/after the instruction.
278  if (!IsDefined)
279  return false;
280 
281  // Otherwise, the Reg is not live before the MI and the MOV can't
282  // make it really live, so it's in fact dead even after the MI.
283  return true;
284 }
285 
286 MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
287  MachineInstr *MI) const {
288  Register NewDestReg;
289 
290  // We are going to try to rewrite this load to a larger zero-extending
291  // load. This is safe if all portions of the 32 bit super-register
292  // of the original destination register, except for the original destination
293  // register are dead. getSuperRegDestIfDead checks that.
294  if (!getSuperRegDestIfDead(MI, NewDestReg))
295  return nullptr;
296 
297  // Safe to change the instruction.
298  MachineInstrBuilder MIB =
299  BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
300 
301  unsigned NumArgs = MI->getNumOperands();
302  for (unsigned i = 1; i < NumArgs; ++i)
303  MIB.add(MI->getOperand(i));
304 
305  MIB.setMemRefs(MI->memoperands());
306 
307  return MIB;
308 }
309 
310 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
311  assert(MI->getNumExplicitOperands() == 2);
312  auto &OldDest = MI->getOperand(0);
313  auto &OldSrc = MI->getOperand(1);
314 
315  Register NewDestReg;
316  if (!getSuperRegDestIfDead(MI, NewDestReg))
317  return nullptr;
318 
319  Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
320 
321  // This is only correct if we access the same subregister index: otherwise,
322  // we could try to replace "movb %ah, %al" with "movl %eax, %eax".
323  auto *TRI = &TII->getRegisterInfo();
324  if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
325  TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
326  return nullptr;
327 
328  // Safe to change the instruction.
329  // Don't set src flags, as we don't know if we're also killing the superreg.
330  // However, the superregister might not be defined; make it explicit that
331  // we don't care about the higher bits by reading it as Undef, and adding
332  // an imp-use on the original subregister.
333  MachineInstrBuilder MIB =
334  BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
335  .addReg(NewSrcReg, RegState::Undef)
336  .addReg(OldSrc.getReg(), RegState::Implicit);
337 
338  // Drop imp-defs/uses that would be redundant with the new def/use.
339  for (auto &Op : MI->implicit_operands())
340  if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
341  MIB.add(Op);
342 
343  return MIB;
344 }
345 
346 MachineInstr *FixupBWInstPass::tryReplaceExtend(unsigned New32BitOpcode,
347  MachineInstr *MI) const {
348  Register NewDestReg;
349  if (!getSuperRegDestIfDead(MI, NewDestReg))
350  return nullptr;
351 
352  // Don't interfere with formation of CBW instructions which should be a
353  // shorter encoding than even the MOVSX32rr8. It's also immune to partial
354  // merge issues on Intel CPUs.
355  if (MI->getOpcode() == X86::MOVSX16rr8 &&
356  MI->getOperand(0).getReg() == X86::AX &&
357  MI->getOperand(1).getReg() == X86::AL)
358  return nullptr;
359 
360  // Safe to change the instruction.
361  MachineInstrBuilder MIB =
362  BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
363 
364  unsigned NumArgs = MI->getNumOperands();
365  for (unsigned i = 1; i < NumArgs; ++i)
366  MIB.add(MI->getOperand(i));
367 
368  MIB.setMemRefs(MI->memoperands());
369 
370  return MIB;
371 }
372 
373 MachineInstr *FixupBWInstPass::tryReplaceInstr(MachineInstr *MI,
374  MachineBasicBlock &MBB) const {
375  // See if this is an instruction of the type we are currently looking for.
376  switch (MI->getOpcode()) {
377 
378  case X86::MOV8rm:
379  // Only replace 8 bit loads with the zero extending versions if
380  // in an inner most loop and not optimizing for size. This takes
381  // an extra byte to encode, and provides limited performance upside.
382  if (MachineLoop *ML = MLI->getLoopFor(&MBB))
383  if (ML->begin() == ML->end() && !OptForSize)
384  return tryReplaceLoad(X86::MOVZX32rm8, MI);
385  break;
386 
387  case X86::MOV16rm:
388  // Always try to replace 16 bit load with 32 bit zero extending.
389  // Code size is the same, and there is sometimes a perf advantage
390  // from eliminating a false dependence on the upper portion of
391  // the register.
392  return tryReplaceLoad(X86::MOVZX32rm16, MI);
393 
394  case X86::MOV8rr:
395  case X86::MOV16rr:
396  // Always try to replace 8/16 bit copies with a 32 bit copy.
397  // Code size is either less (16) or equal (8), and there is sometimes a
398  // perf advantage from eliminating a false dependence on the upper portion
399  // of the register.
400  return tryReplaceCopy(MI);
401 
402  case X86::MOVSX16rr8:
403  return tryReplaceExtend(X86::MOVSX32rr8, MI);
404  case X86::MOVSX16rm8:
405  return tryReplaceExtend(X86::MOVSX32rm8, MI);
406  case X86::MOVZX16rr8:
407  return tryReplaceExtend(X86::MOVZX32rr8, MI);
408  case X86::MOVZX16rm8:
409  return tryReplaceExtend(X86::MOVZX32rm8, MI);
410 
411  default:
412  // nothing to do here.
413  break;
414  }
415 
416  return nullptr;
417 }
418 
419 void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
420  MachineBasicBlock &MBB) {
421 
422  // This algorithm doesn't delete the instructions it is replacing
423  // right away. By leaving the existing instructions in place, the
424  // register liveness information doesn't change, and this makes the
425  // analysis that goes on be better than if the replaced instructions
426  // were immediately removed.
427  //
428  // This algorithm always creates a replacement instruction
429  // and notes that and the original in a data structure, until the
430  // whole BB has been analyzed. This keeps the replacement instructions
431  // from making it seem as if the larger register might be live.
433 
434  // Start computing liveness for this block. We iterate from the end to be able
435  // to update this for each instruction.
436  LiveRegs.clear();
437  // We run after PEI, so we need to AddPristinesAndCSRs.
438  LiveRegs.addLiveOuts(MBB);
439 
440  OptForSize = MF.getFunction().hasOptSize() ||
441  llvm::shouldOptimizeForSize(&MBB, PSI, MBFI);
442 
443  for (auto I = MBB.rbegin(); I != MBB.rend(); ++I) {
444  MachineInstr *MI = &*I;
445 
446  if (MachineInstr *NewMI = tryReplaceInstr(MI, MBB))
447  MIReplacements.push_back(std::make_pair(MI, NewMI));
448 
449  // We're done with this instruction, update liveness for the next one.
450  LiveRegs.stepBackward(*MI);
451  }
452 
453  while (!MIReplacements.empty()) {
454  MachineInstr *MI = MIReplacements.back().first;
455  MachineInstr *NewMI = MIReplacements.back().second;
456  MIReplacements.pop_back();
457  MBB.insert(MI, NewMI);
458  MBB.erase(MI);
459  }
460 }
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand *> MMOs) const
const MachineInstrBuilder & add(const MachineOperand &MO) const
#define FIXUPBW_NAME
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
Definition: Function.h:647
const DebugLoc & getDebugLoc() const
Returns the debug location id of this MachineInstr.
Definition: MachineInstr.h:409
Analysis providing profile information.
#define FIXUPBW_DESC
MachineBlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate machine basic b...
unsigned const TargetRegisterInfo * TRI
MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false)
Returns the sub or super register of a specific X86 register.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineBasicBlock & MBB
AnalysisUsage & addRequired()
instr_iterator erase(instr_iterator I)
Remove an instruction from the instruction list and delete it.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
const HexagonInstrInfo * TII
An analysis pass based on legacy pass manager to deliver ProfileSummaryInfo.
unsigned getNumOperands() const
Retuns the total number of operands.
Definition: MachineInstr.h:459
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:456
===- LazyMachineBlockFrequencyInfo.h - Lazy Block Frequency -*- C++ -*–===//
instr_iterator insert(instr_iterator I, MachineInstr *M)
Insert MI into the instruction list before I, possibly inside a bundle.
reverse_iterator rend()
reverse_iterator rbegin()
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:434
ArrayRef< MachineMemOperand * > memoperands() const
Access to memory operands of the instruction.
Definition: MachineInstr.h:627
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
This is an alternative analysis pass to MachineBlockFrequencyInfo.
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:284
This file implements the LivePhysRegs utility for tracking liveness of physical registers.
unsigned getNumExplicitOperands() const
Returns the number of non-implicit operands.
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:37
static cl::opt< bool > FixupBWInsts("fixup-byte-word-insts", cl::desc("Change byte and word instructions to larger sizes"), cl::init(true), cl::Hidden)
This is a &#39;vector&#39; (really, a variable-sized array), optimized for the case when the array is small...
Definition: SmallVector.h:883
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile...
iterator_range< mop_iterator > implicit_operands()
Definition: MachineInstr.h:573
MachineFunctionProperties & set(Property P)
Representation of each machine instruction.
Definition: MachineInstr.h:62
A set of physical registers with utility functions to track liveness when walking backward/forward th...
Definition: LivePhysRegs.h:48
#define I(x, y, z)
Definition: MD5.cpp:59
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
Register getReg() const
getReg - Returns the register number.
#define LLVM_DEBUG(X)
Definition: Debug.h:122
const MachineOperand & getOperand(unsigned i) const
Definition: MachineInstr.h:466
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
Properties which a MachineFunction may have at a given point in time.
Wrapper class representing virtual and physical registers.
Definition: Register.h:19