LLVM 17.0.0git
HexagonRDFOpt.cpp
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1//===- HexagonRDFOpt.cpp --------------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonInstrInfo.h"
10#include "HexagonSubtarget.h"
12#include "RDFCopy.h"
13#include "RDFDeadCode.h"
14#include "llvm/ADT/DenseMap.h"
15#include "llvm/ADT/STLExtras.h"
16#include "llvm/ADT/SetVector.h"
28#include "llvm/Pass.h"
31#include "llvm/Support/Debug.h"
34#include <cassert>
35#include <limits>
36#include <utility>
37
38using namespace llvm;
39using namespace rdf;
40
41namespace llvm {
42
45
46} // end namespace llvm
47
48static unsigned RDFCount = 0;
49
50static cl::opt<unsigned> RDFLimit("rdf-limit",
51 cl::init(std::numeric_limits<unsigned>::max()));
52static cl::opt<bool> RDFDump("rdf-dump", cl::init(false));
53
54namespace {
55
56 class HexagonRDFOpt : public MachineFunctionPass {
57 public:
58 HexagonRDFOpt() : MachineFunctionPass(ID) {}
59
60 void getAnalysisUsage(AnalysisUsage &AU) const override {
63 AU.setPreservesAll();
65 }
66
67 StringRef getPassName() const override {
68 return "Hexagon RDF optimizations";
69 }
70
71 bool runOnMachineFunction(MachineFunction &MF) override;
72
75 MachineFunctionProperties::Property::NoVRegs);
76 }
77
78 static char ID;
79
80 private:
83 };
84
85struct HexagonCP : public CopyPropagation {
86 HexagonCP(DataFlowGraph &G) : CopyPropagation(G) {}
87
88 bool interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) override;
89};
90
91struct HexagonDCE : public DeadCodeElimination {
94
96 void removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum);
97
98 bool run();
99};
100
101} // end anonymous namespace
102
103char HexagonRDFOpt::ID = 0;
104
105INITIALIZE_PASS_BEGIN(HexagonRDFOpt, "hexagon-rdf-opt",
106 "Hexagon RDF optimizations", false, false)
109INITIALIZE_PASS_END(HexagonRDFOpt, "hexagon-rdf-opt",
110 "Hexagon RDF optimizations", false, false)
111
112bool HexagonCP::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) {
113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void {
114 EM.insert(std::make_pair(DstR, SrcR));
115 };
116
117 DataFlowGraph &DFG = getDFG();
118 unsigned Opc = MI->getOpcode();
119 switch (Opc) {
120 case Hexagon::A2_combinew: {
121 const MachineOperand &DstOp = MI->getOperand(0);
122 const MachineOperand &HiOp = MI->getOperand(1);
123 const MachineOperand &LoOp = MI->getOperand(2);
124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
125 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
127 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
129 return true;
130 }
131 case Hexagon::A2_addi: {
132 const MachineOperand &A = MI->getOperand(2);
133 if (!A.isImm() || A.getImm() != 0)
134 return false;
135 [[fallthrough]];
136 }
137 case Hexagon::A2_tfr: {
138 const MachineOperand &DstOp = MI->getOperand(0);
139 const MachineOperand &SrcOp = MI->getOperand(1);
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
142 return true;
143 }
144 }
145
146 return CopyPropagation::interpretAsCopy(MI, EM);
147}
148
149bool HexagonDCE::run() {
150 bool Collected = collect();
151 if (!Collected)
152 return false;
153
154 const SetVector<NodeId> &DeadNodes = getDeadNodes();
155 const SetVector<NodeId> &DeadInstrs = getDeadInstrs();
156
157 using RefToInstrMap = DenseMap<NodeId, NodeId>;
158
159 RefToInstrMap R2I;
160 SetVector<NodeId> PartlyDead;
161 DataFlowGraph &DFG = getDFG();
162
163 for (NodeAddr<BlockNode*> BA : DFG.getFunc().Addr->members(DFG)) {
164 for (auto TA : BA.Addr->members_if(DFG.IsCode<NodeAttrs::Stmt>, DFG)) {
166 for (NodeAddr<RefNode*> RA : SA.Addr->members(DFG)) {
167 R2I.insert(std::make_pair(RA.Id, SA.Id));
168 if (DFG.IsDef(RA) && DeadNodes.count(RA.Id))
169 if (!DeadInstrs.count(SA.Id))
170 PartlyDead.insert(SA.Id);
171 }
172 }
173 }
174
175 // Nodes to remove.
176 SetVector<NodeId> Remove = DeadInstrs;
177
178 bool Changed = false;
179 for (NodeId N : PartlyDead) {
180 auto SA = DFG.addr<StmtNode*>(N);
181 if (trace())
182 dbgs() << "Partly dead: " << *SA.Addr->getCode();
183 Changed |= rewrite(SA, Remove);
184 }
185
186 return erase(Remove) || Changed;
187}
188
189void HexagonDCE::removeOperand(NodeAddr<InstrNode*> IA, unsigned OpNum) {
190 MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
191
192 auto getOpNum = [MI] (MachineOperand &Op) -> unsigned {
193 for (unsigned i = 0, n = MI->getNumOperands(); i != n; ++i)
194 if (&MI->getOperand(i) == &Op)
195 return i;
196 llvm_unreachable("Invalid operand");
197 };
199 DataFlowGraph &DFG = getDFG();
200 NodeList Refs = IA.Addr->members(DFG);
201 for (NodeAddr<RefNode*> RA : Refs)
202 OpMap.insert(std::make_pair(RA.Id, getOpNum(RA.Addr->getOp())));
203
204 MI->removeOperand(OpNum);
205
206 for (NodeAddr<RefNode*> RA : Refs) {
207 unsigned N = OpMap[RA.Id];
208 if (N < OpNum)
209 RA.Addr->setRegRef(&MI->getOperand(N), DFG);
210 else if (N > OpNum)
211 RA.Addr->setRegRef(&MI->getOperand(N-1), DFG);
212 }
213}
214
215bool HexagonDCE::rewrite(NodeAddr<InstrNode*> IA, SetVector<NodeId> &Remove) {
216 if (!getDFG().IsCode<NodeAttrs::Stmt>(IA))
217 return false;
218 DataFlowGraph &DFG = getDFG();
219 MachineInstr &MI = *NodeAddr<StmtNode*>(IA).Addr->getCode();
220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII());
221 if (HII.getAddrMode(MI) != HexagonII::PostInc)
222 return false;
223 unsigned Opc = MI.getOpcode();
224 unsigned OpNum, NewOpc;
225 switch (Opc) {
226 case Hexagon::L2_loadri_pi:
227 NewOpc = Hexagon::L2_loadri_io;
228 OpNum = 1;
229 break;
230 case Hexagon::L2_loadrd_pi:
231 NewOpc = Hexagon::L2_loadrd_io;
232 OpNum = 1;
233 break;
234 case Hexagon::V6_vL32b_pi:
235 NewOpc = Hexagon::V6_vL32b_ai;
236 OpNum = 1;
237 break;
238 case Hexagon::S2_storeri_pi:
239 NewOpc = Hexagon::S2_storeri_io;
240 OpNum = 0;
241 break;
242 case Hexagon::S2_storerd_pi:
243 NewOpc = Hexagon::S2_storerd_io;
244 OpNum = 0;
245 break;
246 case Hexagon::V6_vS32b_pi:
247 NewOpc = Hexagon::V6_vS32b_ai;
248 OpNum = 0;
249 break;
250 default:
251 return false;
252 }
253 auto IsDead = [this] (NodeAddr<DefNode*> DA) -> bool {
254 return getDeadNodes().count(DA.Id);
255 };
256 NodeList Defs;
257 MachineOperand &Op = MI.getOperand(OpNum);
258 for (NodeAddr<DefNode*> DA : IA.Addr->members_if(DFG.IsDef, DFG)) {
259 if (&DA.Addr->getOp() != &Op)
260 continue;
261 Defs = DFG.getRelatedRefs(IA, DA);
262 if (!llvm::all_of(Defs, IsDead))
263 return false;
264 break;
265 }
266
267 // Mark all nodes in Defs for removal.
268 for (auto D : Defs)
269 Remove.insert(D.Id);
270
271 if (trace())
272 dbgs() << "Rewriting: " << MI;
273 MI.setDesc(HII.get(NewOpc));
274 MI.getOperand(OpNum+2).setImm(0);
275 removeOperand(IA, OpNum);
276 if (trace())
277 dbgs() << " to: " << MI;
278
279 return true;
280}
281
282bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) {
283 if (skipFunction(MF.getFunction()))
284 return false;
285
286 if (RDFLimit.getPosition()) {
287 if (RDFCount >= RDFLimit)
288 return false;
289 RDFCount++;
290 }
291
292 MDT = &getAnalysis<MachineDominatorTree>();
293 const auto &MDF = getAnalysis<MachineDominanceFrontier>();
294 const auto &HII = *MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
295 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
296 MRI = &MF.getRegInfo();
297 bool Changed;
298
299 if (RDFDump)
300 MF.print(dbgs() << "Before " << getPassName() << "\n", nullptr);
301
302 DataFlowGraph G(MF, HII, HRI, *MDT, MDF);
303 // Dead phi nodes are necessary for copy propagation: we can add a use
304 // of a register in a block where it would need a phi node, but which
305 // was dead (and removed) during the graph build time.
307
308 if (RDFDump)
309 dbgs() << "Starting copy propagation on: " << MF.getName() << '\n'
310 << PrintNode<FuncNode*>(G.getFunc(), G) << '\n';
311 HexagonCP CP(G);
312 CP.trace(RDFDump);
313 Changed = CP.run();
314
315 if (RDFDump)
316 dbgs() << "Starting dead code elimination on: " << MF.getName() << '\n'
317 << PrintNode<FuncNode*>(G.getFunc(), G) << '\n';
318 HexagonDCE DCE(G, *MRI);
319 DCE.trace(RDFDump);
320 Changed |= DCE.run();
321
322 if (Changed) {
323 if (RDFDump)
324 dbgs() << "Starting liveness recomputation on: " << MF.getName() << '\n';
325 Liveness LV(*MRI, G);
326 LV.trace(RDFDump);
327 LV.computeLiveIns();
328 LV.resetLiveIns();
329 LV.resetKills();
330 }
331
332 if (RDFDump)
333 MF.print(dbgs() << "After " << getPassName() << "\n", nullptr);
334
335 return false;
336}
337
339 return new HexagonRDFOpt();
340}
unsigned const MachineRegisterInfo * MRI
aarch64 promote const
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
This file defines the DenseMap class.
static cl::opt< unsigned > RDFLimit("rdf-limit", cl::init(std::numeric_limits< unsigned >::max()))
hexagon rdf Hexagon RDF optimizations
static cl::opt< bool > RDFDump("rdf-dump", cl::init(false))
hexagon rdf opt
static unsigned RDFCount
IRTranslator LLVM IR MI
#define G(x, y, z)
Definition: MD5.cpp:56
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
static bool rewrite(Function &F)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
bool IsDead
SI optimize exec mask operations pre RA
This file contains some templates that are useful if you are working with the STL at all.
This file implements a set that has insertion order iteration characteristics.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
void setPreservesAll()
Set by analyses that do not transform their input at all.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Definition: DenseMap.h:207
Register getReg() const
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
virtual MachineFunctionProperties getRequiredProperties() const
Properties which a MachineFunction may have at a given point in time.
MachineFunctionProperties & set(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
Representation of each machine instruction.
Definition: MachineInstr.h:68
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
Register getReg() const
getReg - Returns the register number.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Definition: Pass.cpp:81
A vector that has set insertion semantics.
Definition: SetVector.h:40
size_type count(const key_type &key) const
Count the number of elements of a given key in the SetVector.
Definition: SetVector.h:208
bool insert(const value_type &X)
Insert a new element into the SetVector.
Definition: SetVector.h:141
Register getReg() const
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
PointerTypeMap run(const Module &M)
Compute the PointerTypeMap for the module M.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1735
void initializeHexagonRDFOptPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
FunctionPass * createHexagonRDFOpt()
#define N
NodeAddr< FuncNode * > getFunc() const
Definition: RDFGraph.h:664
const TargetInstrInfo & getTII() const
Definition: RDFGraph.h:666
RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const
Definition: RDFGraph.cpp:967
static bool IsDef(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:796
static bool IsCode(const NodeAddr< NodeBase * > BA)
Definition: RDFGraph.h:791
NodeList getRelatedRefs(NodeAddr< InstrNode * > IA, NodeAddr< RefNode * > RA) const
Definition: RDFGraph.cpp:1114
NodeAddr< T > addr(NodeId N) const
Definition: RDFGraph.h:660