LLVM  16.0.0git
NVPTXTargetMachine.cpp
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1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the NVPTX target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "NVPTXTargetMachine.h"
14 #include "NVPTX.h"
15 #include "NVPTXAllocaHoisting.h"
16 #include "NVPTXAtomicLower.h"
17 #include "NVPTXLowerAggrCopies.h"
18 #include "NVPTXTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/IntrinsicsNVPTX.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/Pass.h"
34 #include "llvm/Transforms/Scalar.h"
37 #include <cassert>
38 #include <string>
39 
40 using namespace llvm;
41 
42 // LSV is still relatively new; this switch lets us turn it off in case we
43 // encounter (or suspect) a bug.
44 static cl::opt<bool>
45  DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
46  cl::desc("Disable load/store vectorizer"),
47  cl::init(false), cl::Hidden);
48 
49 // TODO: Remove this flag when we are confident with no regressions.
51  "disable-nvptx-require-structured-cfg",
52  cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
53  "structured CFG. The requirement should be disabled only when "
54  "unexpected regressions happen."),
55  cl::init(false), cl::Hidden);
56 
58  "nvptx-short-ptr",
59  cl::desc(
60  "Use 32-bit pointers for accessing const/local/shared address spaces."),
61  cl::init(false), cl::Hidden);
62 
63 namespace llvm {
64 
75 
76 } // end namespace llvm
77 
79  // Register the target.
82 
83  // FIXME: This pass is really intended to be invoked during IR optimization,
84  // but it's very NVPTX-specific.
96 }
97 
98 static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
99  std::string Ret = "e";
100 
101  if (!is64Bit)
102  Ret += "-p:32:32";
103  else if (UseShortPointers)
104  Ret += "-p3:32:32-p4:32:32-p5:32:32";
105 
106  Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
107 
108  return Ret;
109 }
110 
112  StringRef CPU, StringRef FS,
113  const TargetOptions &Options,
116  CodeGenOpt::Level OL, bool is64bit)
117  // The pic relocation model is used regardless of what the client has
118  // specified, as it is the only relocation model currently supported.
120  CPU, FS, Options, Reloc::PIC_,
122  is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
123  TLOF(std::make_unique<NVPTXTargetObjectFile>()),
124  Subtarget(TT, std::string(CPU), std::string(FS), *this) {
125  if (TT.getOS() == Triple::NVCL)
126  drvInterface = NVPTX::NVCL;
127  else
128  drvInterface = NVPTX::CUDA;
131  initAsmInfo();
132 }
133 
135 
136 void NVPTXTargetMachine32::anchor() {}
137 
139  StringRef CPU, StringRef FS,
140  const TargetOptions &Options,
143  CodeGenOpt::Level OL, bool JIT)
144  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
145 
146 void NVPTXTargetMachine64::anchor() {}
147 
149  StringRef CPU, StringRef FS,
150  const TargetOptions &Options,
153  CodeGenOpt::Level OL, bool JIT)
154  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
155 
156 namespace {
157 
158 class NVPTXPassConfig : public TargetPassConfig {
159 public:
160  NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
161  : TargetPassConfig(TM, PM) {}
162 
163  NVPTXTargetMachine &getNVPTXTargetMachine() const {
164  return getTM<NVPTXTargetMachine>();
165  }
166 
167  void addIRPasses() override;
168  bool addInstSelector() override;
169  void addPreRegAlloc() override;
170  void addPostRegAlloc() override;
171  void addMachineSSAOptimization() override;
172 
173  FunctionPass *createTargetRegisterAllocator(bool) override;
174  void addFastRegAlloc() override;
175  void addOptimizedRegAlloc() override;
176 
177  bool addRegAssignAndRewriteFast() override {
178  llvm_unreachable("should not be used");
179  }
180 
181  bool addRegAssignAndRewriteOptimized() override {
182  llvm_unreachable("should not be used");
183  }
184 
185 private:
186  // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
187  // function is only called in opt mode.
188  void addEarlyCSEOrGVNPass();
189 
190  // Add passes that propagate special memory spaces.
191  void addAddressSpaceInferencePasses();
192 
193  // Add passes that perform straight-line scalar optimizations.
194  void addStraightLineScalarOptimizationPasses();
195 };
196 
197 } // end anonymous namespace
198 
200  return new NVPTXPassConfig(*this, PM);
201 }
202 
207  if (PassName == "nvvm-reflect") {
208  PM.addPass(NVVMReflectPass());
209  return true;
210  }
211  if (PassName == "nvvm-intr-range") {
213  return true;
214  }
215  return false;
216  });
217 
219  [this](ModulePassManager &PM, OptimizationLevel Level) {
221  FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
222  // FIXME: NVVMIntrRangePass is causing numerical discrepancies,
223  // investigate and re-enable.
224  // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
226  });
227 }
228 
231  return TargetTransformInfo(NVPTXTTIImpl(this, F));
232 }
233 
234 std::pair<const Value *, unsigned>
236  if (auto *II = dyn_cast<IntrinsicInst>(V)) {
237  switch (II->getIntrinsicID()) {
238  case Intrinsic::nvvm_isspacep_const:
239  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_CONST);
240  case Intrinsic::nvvm_isspacep_global:
241  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_GLOBAL);
242  case Intrinsic::nvvm_isspacep_local:
243  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_LOCAL);
244  case Intrinsic::nvvm_isspacep_shared:
245  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_SHARED);
246  default:
247  break;
248  }
249  }
250  return std::make_pair(nullptr, -1);
251 }
252 
253 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
254  if (getOptLevel() == CodeGenOpt::Aggressive)
255  addPass(createGVNPass());
256  else
257  addPass(createEarlyCSEPass());
258 }
259 
260 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
261  // NVPTXLowerArgs emits alloca for byval parameters which can often
262  // be eliminated by SROA.
263  addPass(createSROAPass());
264  addPass(createNVPTXLowerAllocaPass());
265  addPass(createInferAddressSpacesPass());
266  addPass(createNVPTXAtomicLowerPass());
267 }
268 
269 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
272  // ReassociateGEPs exposes more opportunites for SLSR. See
273  // the example in reassociate-geps-and-slsr.ll.
275  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
276  // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
277  // for some of our benchmarks.
278  addEarlyCSEOrGVNPass();
279  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
280  addPass(createNaryReassociatePass());
281  // NaryReassociate on GEPs creates redundant common expressions, so run
282  // EarlyCSE after it.
283  addPass(createEarlyCSEPass());
284 }
285 
286 void NVPTXPassConfig::addIRPasses() {
287  // The following passes are known to not play well with virtual regs hanging
288  // around after register allocation (which in our case, is *all* registers).
289  // We explicitly disable them here. We do, however, need some functionality
290  // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
291  // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
292  disablePass(&PrologEpilogCodeInserterID);
293  disablePass(&MachineCopyPropagationID);
294  disablePass(&TailDuplicateID);
295  disablePass(&StackMapLivenessID);
296  disablePass(&LiveDebugValuesID);
297  disablePass(&PostRAMachineSinkingID);
298  disablePass(&PostRASchedulerID);
299  disablePass(&FuncletLayoutID);
300  disablePass(&PatchableFunctionID);
301  disablePass(&ShrinkWrapID);
302 
303  // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
304  // it here does nothing. But since we need it for correctness when lowering
305  // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
306  // call addEarlyAsPossiblePasses.
307  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
308  addPass(createNVVMReflectPass(ST.getSmVersion()));
309 
310  if (getOptLevel() != CodeGenOpt::None)
313  addPass(createGenericToNVVMPass());
314 
315  // NVPTXLowerArgs is required for correctness and should be run right
316  // before the address space inference passes.
317  addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
318  if (getOptLevel() != CodeGenOpt::None) {
319  addAddressSpaceInferencePasses();
320  addStraightLineScalarOptimizationPasses();
321  }
322 
323  addPass(createAtomicExpandPass());
324 
325  // === LSR and other generic IR passes ===
327  // EarlyCSE is not always strong enough to clean up what LSR produces. For
328  // example, GVN can combine
329  //
330  // %0 = add %a, %b
331  // %1 = add %b, %a
332  //
333  // and
334  //
335  // %0 = shl nsw %a, 2
336  // %1 = shl %a, 2
337  //
338  // but EarlyCSE can do neither of them.
339  if (getOptLevel() != CodeGenOpt::None) {
340  addEarlyCSEOrGVNPass();
343  addPass(createSROAPass());
344  }
345 }
346 
347 bool NVPTXPassConfig::addInstSelector() {
348  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
349 
350  addPass(createLowerAggrCopies());
351  addPass(createAllocaHoisting());
352  addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
353 
354  if (!ST.hasImageHandles())
356 
357  return false;
358 }
359 
360 void NVPTXPassConfig::addPreRegAlloc() {
361  // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
363 }
364 
365 void NVPTXPassConfig::addPostRegAlloc() {
366  addPass(createNVPTXPrologEpilogPass());
367  if (getOptLevel() != CodeGenOpt::None) {
368  // NVPTXPrologEpilogPass calculates frame object offset and replace frame
369  // index with VRFrame register. NVPTXPeephole need to be run after that and
370  // will replace VRFrame with VRFrameLocal when possible.
371  addPass(createNVPTXPeephole());
372  }
373 }
374 
375 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
376  return nullptr; // No reg alloc
377 }
378 
379 void NVPTXPassConfig::addFastRegAlloc() {
380  addPass(&PHIEliminationID);
381  addPass(&TwoAddressInstructionPassID);
382 }
383 
384 void NVPTXPassConfig::addOptimizedRegAlloc() {
385  addPass(&ProcessImplicitDefsID);
386  addPass(&LiveVariablesID);
387  addPass(&MachineLoopInfoID);
388  addPass(&PHIEliminationID);
389 
390  addPass(&TwoAddressInstructionPassID);
391  addPass(&RegisterCoalescerID);
392 
393  // PreRA instruction scheduling.
394  if (addPass(&MachineSchedulerID))
395  printAndVerify("After Machine Scheduling");
396 
397 
398  addPass(&StackSlotColoringID);
399 
400  // FIXME: Needs physical registers
401  //addPass(&MachineLICMID);
402 
403  printAndVerify("After StackSlotColoring");
404 }
405 
406 void NVPTXPassConfig::addMachineSSAOptimization() {
407  // Pre-ra tail duplication.
408  if (addPass(&EarlyTailDuplicateID))
409  printAndVerify("After Pre-RegAlloc TailDuplicate");
410 
411  // Optimize PHIs before DCE: removing dead PHI cycles may make more
412  // instructions dead.
413  addPass(&OptimizePHIsID);
414 
415  // This pass merges large allocas. StackSlotColoring is a different pass
416  // which merges spill slots.
417  addPass(&StackColoringID);
418 
419  // If the target requests it, assign local variables to stack slots relative
420  // to one another and simplify frame index references where possible.
421  addPass(&LocalStackSlotAllocationID);
422 
423  // With optimization, dead code should already be eliminated. However
424  // there is one known exception: lowered code for arguments that are only
425  // used by tail calls, where the tail calls reuse the incoming stack
426  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
428  printAndVerify("After codegen DCE pass");
429 
430  // Allow targets to insert passes that improve instruction level parallelism,
431  // like if-conversion. Such passes will typically need dominator trees and
432  // loop info, just like LICM and CSE below.
433  if (addILPOpts())
434  printAndVerify("After ILP optimizations");
435 
436  addPass(&EarlyMachineLICMID);
437  addPass(&MachineCSEID);
438 
439  addPass(&MachineSinkingID);
440  printAndVerify("After Machine LICM, CSE and Sinking passes");
441 
442  addPass(&PeepholeOptimizerID);
443  printAndVerify("After codegen peephole optimization pass");
444 }
llvm::OptimizePHIsID
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
Definition: OptimizePHIs.cpp:68
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
PassBuilder.h
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:498
llvm::NVPTXTargetMachine::~NVPTXTargetMachine
~NVPTXTargetMachine() override
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:455
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
llvm::Function
Definition: Function.h:60
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:544
Pass.h
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:128
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1018
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:149
llvm::ADDRESS_SPACE_LOCAL
@ ADDRESS_SPACE_LOCAL
Definition: NVPTXBaseInfo.h:26
llvm::initializeNVPTXAllocaHoistingPass
void initializeNVPTXAllocaHoistingPass(PassRegistry &)
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:173
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::NVPTXSubtarget::getSmVersion
unsigned int getSmVersion() const
Definition: NVPTXSubtarget.h:81
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1790
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:140
llvm::createNVPTXReplaceImageHandlesPass
MachineFunctionPass * createNVPTXReplaceImageHandlesPass()
Definition: NVPTXReplaceImageHandles.cpp:1847
llvm::NVPTXTargetMachine32::NVPTXTargetMachine32
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: NVPTXTargetMachine.cpp:138
UseShortPointersOpt
static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1793
llvm::initializeNVPTXProxyRegErasurePass
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
llvm::LocalStackSlotAllocationID
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
Definition: LocalStackSlotAllocation.cpp:108
llvm::X86AS::FS
@ FS
Definition: X86.h:200
llvm::Optional< Reloc::Model >
T
#define T
Definition: Mips16ISelLowering.cpp:341
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3244
llvm::createNVPTXLowerArgsPass
FunctionPass * createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM)
Definition: NVPTXLowerArgs.cpp:469
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
STLExtras.h
llvm::StackSlotColoringID
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
Definition: StackSlotColoring.cpp:131
llvm::initializeNVPTXAtomicLowerPass
void initializeNVPTXAtomicLowerPass(PassRegistry &)
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:354
NVPTXTargetTransformInfo.h
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:193
llvm::createNVPTXAssignValidGlobalNamesPass
ModulePass * createNVPTXAssignValidGlobalNamesPass()
Definition: NVPTXAssignValidGlobalNames.cpp:86
llvm::NVPTXTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: NVPTXTargetMachine.cpp:230
llvm::NVPTXTargetMachine
NVPTXTargetMachine.
Definition: NVPTXTargetMachine.h:25
computeDataLayout
static std::string computeDataLayout(bool is64Bit, bool UseShortPointers)
Definition: NVPTXTargetMachine.cpp:98
F
#define F(x, y, z)
Definition: MD5.cpp:55
NVPTX.h
NVPTXTargetInfo.h
CommandLine.h
llvm::initializeNVPTXLowerAllocaPass
void initializeNVPTXLowerAllocaPass(PassRegistry &)
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:95
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1309
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:24
llvm::NVVMIntrRangePass
Definition: NVPTX.h:51
llvm::PrologEpilogCodeInserterID
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
Definition: PrologEpilogInserter.cpp:150
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::initializeNVPTXLowerAggrCopiesPass
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)
llvm::ADDRESS_SPACE_GLOBAL
@ ADDRESS_SPACE_GLOBAL
Definition: NVPTXBaseInfo.h:23
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:97
llvm::createLowerAggrCopies
FunctionPass * createLowerAggrCopies()
NVPTXAtomicLower.h
false
Definition: StackSlotColoring.cpp:141
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:405
llvm::NVPTXTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline.
Definition: NVPTXTargetMachine.cpp:203
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::ADDRESS_SPACE_CONST
@ ADDRESS_SPACE_CONST
Definition: NVPTXBaseInfo.h:25
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1356
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createNVPTXPrologEpilogPass
MachineFunctionPass * createNVPTXPrologEpilogPass()
Definition: NVPTXPrologEpilogPass.cpp:46
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::NVPTXTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: NVPTXTargetMachine.cpp:199
GVN.h
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::NVPTX::NVCL
@ NVCL
Definition: NVPTX.h:71
llvm::getTheNVPTXTarget64
Target & getTheNVPTXTarget64()
Definition: NVPTXTargetInfo.cpp:17
llvm::EarlyTailDuplicateID
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:77
llvm::NVPTXSubtarget
Definition: NVPTXSubtarget.h:31
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::NVPTXTTIImpl
Definition: NVPTXTargetTransformInfo.h:27
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:43
llvm::cl::opt< bool >
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1218
llvm::StackColoringID
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Definition: StackColoring.cpp:549
llvm::NVPTXTargetMachine::NVPTXTargetMachine
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OP, bool is64bit)
Definition: NVPTXTargetMachine.cpp:111
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:216
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
llvm::MachineSinkingID
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
Definition: MachineSink.cpp:260
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::Triple::NVCL
@ NVCL
Definition: Triple.h:209
llvm::createNVVMReflectPass
FunctionPass * createNVVMReflectPass(unsigned int SmVersion)
Definition: NVVMReflect.cpp:64
NVPTXAllocaHoisting.h
llvm::NVPTXTargetMachine::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
Definition: NVPTXTargetMachine.cpp:235
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:854
llvm::createNVPTXAtomicLowerPass
FunctionPass * createNVPTXAtomicLowerPass()
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:447
llvm::ADDRESS_SPACE_SHARED
@ ADDRESS_SPACE_SHARED
Definition: NVPTXBaseInfo.h:24
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
TargetPassConfig.h
llvm::NVPTXTargetObjectFile
Definition: NVPTXTargetObjectFile.h:18
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:162
NVPTXLowerAggrCopies.h
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:58
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:537
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createNVPTXISelDag
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...
Definition: NVPTXISelDAGToDAG.cpp:33
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:487
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:143
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::initializeNVVMReflectPass
void initializeNVVMReflectPass(PassRegistry &)
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:500
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
DisableLoadStoreVectorizer
static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)
llvm::initializeGenericToNVVMPass
void initializeGenericToNVVMPass(PassRegistry &)
llvm::PassManager< Function >
llvm::NVPTXTargetMachine64::NVPTXTargetMachine64
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: NVPTXTargetMachine.cpp:148
std
Definition: BitVector.h:851
llvm::NVPTX::CUDA
@ CUDA
Definition: NVPTX.h:72
llvm::NVVMReflectPass
Definition: NVPTX.h:60
NVPTXTargetMachine.h
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::TailDuplicateID
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:76
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:408
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:56
llvm::createNVPTXImageOptimizerPass
FunctionPass * createNVPTXImageOptimizerPass()
Definition: NVPTXImageOptimizer.cpp:175
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:212
DisableRequireStructuredCFG
static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)
llvm::createGenericToNVVMPass
ModulePass * createGenericToNVVMPass()
Definition: NVPTXGenericToNVVM.cpp:64
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:197
LLVMInitializeNVPTXTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()
Definition: NVPTXTargetMachine.cpp:78
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:268
NVPTXTargetObjectFile.h
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::initializeNVPTXLowerArgsPass
void initializeNVPTXLowerArgsPass(PassRegistry &)
Vectorize.h
llvm::createNVPTXProxyRegErasurePass
MachineFunctionPass * createNVPTXProxyRegErasurePass()
Definition: NVPTXProxyRegErasure.cpp:121
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::createNVPTXPeephole
MachineFunctionPass * createNVPTXPeephole()
Definition: NVPTXPeephole.cpp:167
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:297
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1622
llvm::cl::desc
Definition: CommandLine.h:413
llvm::createNVPTXLowerAllocaPass
FunctionPass * createNVPTXLowerAllocaPass()
Definition: NVPTXLowerAlloca.cpp:115
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:5062
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::initializeNVPTXAssignValidGlobalNamesPass
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:671
llvm::initializeNVVMIntrRangePass
void initializeNVVMIntrRangePass(PassRegistry &)
SpecialSubKind::string
@ string
llvm::createAllocaHoisting
FunctionPass * createAllocaHoisting()
llvm::getTheNVPTXTarget32
Target & getTheNVPTXTarget32()
Definition: NVPTXTargetInfo.cpp:13