LLVM  14.0.0git
NVPTXTargetMachine.cpp
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1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Top-level implementation for the NVPTX target.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "NVPTXTargetMachine.h"
14 #include "NVPTX.h"
15 #include "NVPTXAllocaHoisting.h"
16 #include "NVPTXAtomicLower.h"
17 #include "NVPTXLowerAggrCopies.h"
18 #include "NVPTXTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/IntrinsicsNVPTX.h"
28 #include "llvm/MC/TargetRegistry.h"
29 #include "llvm/Pass.h"
35 #include "llvm/Transforms/Scalar.h"
38 #include <cassert>
39 #include <string>
40 
41 using namespace llvm;
42 
43 // LSV is still relatively new; this switch lets us turn it off in case we
44 // encounter (or suspect) a bug.
45 static cl::opt<bool>
46  DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
47  cl::desc("Disable load/store vectorizer"),
48  cl::init(false), cl::Hidden);
49 
50 // TODO: Remove this flag when we are confident with no regressions.
52  "disable-nvptx-require-structured-cfg",
53  cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
54  "structured CFG. The requirement should be disabled only when "
55  "unexpected regressions happen."),
56  cl::init(false), cl::Hidden);
57 
59  "nvptx-short-ptr",
60  cl::desc(
61  "Use 32-bit pointers for accessing const/local/shared address spaces."),
62  cl::init(false), cl::Hidden);
63 
64 namespace llvm {
65 
76 
77 } // end namespace llvm
78 
80  // Register the target.
83 
84  // FIXME: This pass is really intended to be invoked during IR optimization,
85  // but it's very NVPTX-specific.
97 }
98 
99 static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
100  std::string Ret = "e";
101 
102  if (!is64Bit)
103  Ret += "-p:32:32";
104  else if (UseShortPointers)
105  Ret += "-p3:32:32-p4:32:32-p5:32:32";
106 
107  Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
108 
109  return Ret;
110 }
111 
113  StringRef CPU, StringRef FS,
114  const TargetOptions &Options,
117  CodeGenOpt::Level OL, bool is64bit)
118  // The pic relocation model is used regardless of what the client has
119  // specified, as it is the only relocation model currently supported.
121  CPU, FS, Options, Reloc::PIC_,
123  is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
124  TLOF(std::make_unique<NVPTXTargetObjectFile>()),
125  Subtarget(TT, std::string(CPU), std::string(FS), *this) {
126  if (TT.getOS() == Triple::NVCL)
127  drvInterface = NVPTX::NVCL;
128  else
129  drvInterface = NVPTX::CUDA;
132  initAsmInfo();
133 }
134 
136 
137 void NVPTXTargetMachine32::anchor() {}
138 
140  StringRef CPU, StringRef FS,
141  const TargetOptions &Options,
144  CodeGenOpt::Level OL, bool JIT)
145  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
146 
147 void NVPTXTargetMachine64::anchor() {}
148 
150  StringRef CPU, StringRef FS,
151  const TargetOptions &Options,
154  CodeGenOpt::Level OL, bool JIT)
155  : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
156 
157 namespace {
158 
159 class NVPTXPassConfig : public TargetPassConfig {
160 public:
161  NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
162  : TargetPassConfig(TM, PM) {}
163 
164  NVPTXTargetMachine &getNVPTXTargetMachine() const {
165  return getTM<NVPTXTargetMachine>();
166  }
167 
168  void addIRPasses() override;
169  bool addInstSelector() override;
170  void addPreRegAlloc() override;
171  void addPostRegAlloc() override;
172  void addMachineSSAOptimization() override;
173 
174  FunctionPass *createTargetRegisterAllocator(bool) override;
175  void addFastRegAlloc() override;
176  void addOptimizedRegAlloc() override;
177 
178  bool addRegAssignAndRewriteFast() override {
179  llvm_unreachable("should not be used");
180  }
181 
182  bool addRegAssignAndRewriteOptimized() override {
183  llvm_unreachable("should not be used");
184  }
185 
186 private:
187  // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
188  // function is only called in opt mode.
189  void addEarlyCSEOrGVNPass();
190 
191  // Add passes that propagate special memory spaces.
192  void addAddressSpaceInferencePasses();
193 
194  // Add passes that perform straight-line scalar optimizations.
195  void addStraightLineScalarOptimizationPasses();
196 };
197 
198 } // end anonymous namespace
199 
201  return new NVPTXPassConfig(*this, PM);
202 }
203 
205  Builder.addExtension(
207  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
208  PM.add(createNVVMReflectPass(Subtarget.getSmVersion()));
209  PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
210  });
211 }
212 
217  if (PassName == "nvvm-reflect") {
218  PM.addPass(NVVMReflectPass());
219  return true;
220  }
221  if (PassName == "nvvm-intr-range") {
223  return true;
224  }
225  return false;
226  });
227 
231  FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
232  // FIXME: NVVMIntrRangePass is causing numerical discrepancies,
233  // investigate and re-enable.
234  // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
236  });
237 }
238 
241  return TargetTransformInfo(NVPTXTTIImpl(this, F));
242 }
243 
244 std::pair<const Value *, unsigned>
246  if (auto *II = dyn_cast<IntrinsicInst>(V)) {
247  switch (II->getIntrinsicID()) {
248  case Intrinsic::nvvm_isspacep_const:
249  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_CONST);
250  case Intrinsic::nvvm_isspacep_global:
251  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_GLOBAL);
252  case Intrinsic::nvvm_isspacep_local:
253  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_LOCAL);
254  case Intrinsic::nvvm_isspacep_shared:
255  return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_SHARED);
256  default:
257  break;
258  }
259  }
260  return std::make_pair(nullptr, -1);
261 }
262 
263 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
264  if (getOptLevel() == CodeGenOpt::Aggressive)
265  addPass(createGVNPass());
266  else
267  addPass(createEarlyCSEPass());
268 }
269 
270 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
271  // NVPTXLowerArgs emits alloca for byval parameters which can often
272  // be eliminated by SROA.
273  addPass(createSROAPass());
274  addPass(createNVPTXLowerAllocaPass());
275  addPass(createInferAddressSpacesPass());
276  addPass(createNVPTXAtomicLowerPass());
277 }
278 
279 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
282  // ReassociateGEPs exposes more opportunites for SLSR. See
283  // the example in reassociate-geps-and-slsr.ll.
285  // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
286  // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
287  // for some of our benchmarks.
288  addEarlyCSEOrGVNPass();
289  // Run NaryReassociate after EarlyCSE/GVN to be more effective.
290  addPass(createNaryReassociatePass());
291  // NaryReassociate on GEPs creates redundant common expressions, so run
292  // EarlyCSE after it.
293  addPass(createEarlyCSEPass());
294 }
295 
296 void NVPTXPassConfig::addIRPasses() {
297  // The following passes are known to not play well with virtual regs hanging
298  // around after register allocation (which in our case, is *all* registers).
299  // We explicitly disable them here. We do, however, need some functionality
300  // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
301  // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
302  disablePass(&PrologEpilogCodeInserterID);
303  disablePass(&MachineCopyPropagationID);
304  disablePass(&TailDuplicateID);
305  disablePass(&StackMapLivenessID);
306  disablePass(&LiveDebugValuesID);
307  disablePass(&PostRAMachineSinkingID);
308  disablePass(&PostRASchedulerID);
309  disablePass(&FuncletLayoutID);
310  disablePass(&PatchableFunctionID);
311  disablePass(&ShrinkWrapID);
312 
313  // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
314  // it here does nothing. But since we need it for correctness when lowering
315  // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
316  // call addEarlyAsPossiblePasses.
317  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
318  addPass(createNVVMReflectPass(ST.getSmVersion()));
319 
320  if (getOptLevel() != CodeGenOpt::None)
323  addPass(createGenericToNVVMPass());
324 
325  // NVPTXLowerArgs is required for correctness and should be run right
326  // before the address space inference passes.
327  addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
328  if (getOptLevel() != CodeGenOpt::None) {
329  addAddressSpaceInferencePasses();
330  addStraightLineScalarOptimizationPasses();
331  }
332 
333  // === LSR and other generic IR passes ===
335  // EarlyCSE is not always strong enough to clean up what LSR produces. For
336  // example, GVN can combine
337  //
338  // %0 = add %a, %b
339  // %1 = add %b, %a
340  //
341  // and
342  //
343  // %0 = shl nsw %a, 2
344  // %1 = shl %a, 2
345  //
346  // but EarlyCSE can do neither of them.
347  if (getOptLevel() != CodeGenOpt::None) {
348  addEarlyCSEOrGVNPass();
351  addPass(createSROAPass());
352  }
353 }
354 
355 bool NVPTXPassConfig::addInstSelector() {
356  const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
357 
358  addPass(createLowerAggrCopies());
359  addPass(createAllocaHoisting());
360  addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
361 
362  if (!ST.hasImageHandles())
364 
365  return false;
366 }
367 
368 void NVPTXPassConfig::addPreRegAlloc() {
369  // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
371 }
372 
373 void NVPTXPassConfig::addPostRegAlloc() {
374  addPass(createNVPTXPrologEpilogPass());
375  if (getOptLevel() != CodeGenOpt::None) {
376  // NVPTXPrologEpilogPass calculates frame object offset and replace frame
377  // index with VRFrame register. NVPTXPeephole need to be run after that and
378  // will replace VRFrame with VRFrameLocal when possible.
379  addPass(createNVPTXPeephole());
380  }
381 }
382 
383 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
384  return nullptr; // No reg alloc
385 }
386 
387 void NVPTXPassConfig::addFastRegAlloc() {
388  addPass(&PHIEliminationID);
389  addPass(&TwoAddressInstructionPassID);
390 }
391 
392 void NVPTXPassConfig::addOptimizedRegAlloc() {
393  addPass(&ProcessImplicitDefsID);
394  addPass(&LiveVariablesID);
395  addPass(&MachineLoopInfoID);
396  addPass(&PHIEliminationID);
397 
398  addPass(&TwoAddressInstructionPassID);
399  addPass(&RegisterCoalescerID);
400 
401  // PreRA instruction scheduling.
402  if (addPass(&MachineSchedulerID))
403  printAndVerify("After Machine Scheduling");
404 
405 
406  addPass(&StackSlotColoringID);
407 
408  // FIXME: Needs physical registers
409  //addPass(&MachineLICMID);
410 
411  printAndVerify("After StackSlotColoring");
412 }
413 
414 void NVPTXPassConfig::addMachineSSAOptimization() {
415  // Pre-ra tail duplication.
416  if (addPass(&EarlyTailDuplicateID))
417  printAndVerify("After Pre-RegAlloc TailDuplicate");
418 
419  // Optimize PHIs before DCE: removing dead PHI cycles may make more
420  // instructions dead.
421  addPass(&OptimizePHIsID);
422 
423  // This pass merges large allocas. StackSlotColoring is a different pass
424  // which merges spill slots.
425  addPass(&StackColoringID);
426 
427  // If the target requests it, assign local variables to stack slots relative
428  // to one another and simplify frame index references where possible.
429  addPass(&LocalStackSlotAllocationID);
430 
431  // With optimization, dead code should already be eliminated. However
432  // there is one known exception: lowered code for arguments that are only
433  // used by tail calls, where the tail calls reuse the incoming stack
434  // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
436  printAndVerify("After codegen DCE pass");
437 
438  // Allow targets to insert passes that improve instruction level parallelism,
439  // like if-conversion. Such passes will typically need dominator trees and
440  // loop info, just like LICM and CSE below.
441  if (addILPOpts())
442  printAndVerify("After ILP optimizations");
443 
444  addPass(&EarlyMachineLICMID);
445  addPass(&MachineCSEID);
446 
447  addPass(&MachineSinkingID);
448  printAndVerify("After Machine LICM, CSE and Sinking passes");
449 
450  addPass(&PeepholeOptimizerID);
451  printAndVerify("After codegen peephole optimization pass");
452 }
llvm::OptimizePHIsID
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
Definition: OptimizePHIs.cpp:69
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AllocatorList.h:23
PassBuilder.h
llvm::createSeparateConstOffsetFromGEPPass
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
Definition: SeparateConstOffsetFromGEP.cpp:499
llvm::NVPTXTargetMachine::~NVPTXTargetMachine
~NVPTXTargetMachine() override
llvm::X86AS::FS
@ FS
Definition: X86.h:188
llvm::PeepholeOptimizerID
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
Definition: PeepholeOptimizer.cpp:443
llvm::PassBuilder::registerPipelineStartEPCallback
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:457
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::Function
Definition: Function.h:62
llvm::PassManager::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:553
Pass.h
llvm::PHIEliminationID
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
Definition: PHIElimination.cpp:130
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1019
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:137
llvm::ADDRESS_SPACE_LOCAL
@ ADDRESS_SPACE_LOCAL
Definition: NVPTXBaseInfo.h:26
llvm::initializeNVPTXAllocaHoistingPass
void initializeNVPTXAllocaHoistingPass(PassRegistry &)
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:169
llvm::NVPTXTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
Definition: NVPTXTargetMachine.cpp:240
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
llvm::NVPTXSubtarget::getSmVersion
unsigned int getSmVersion() const
Definition: NVPTXSubtarget.h:80
llvm::createEarlyCSEPass
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1735
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:143
llvm::createNVPTXReplaceImageHandlesPass
MachineFunctionPass * createNVPTXReplaceImageHandlesPass()
Definition: NVPTXReplaceImageHandles.cpp:1843
llvm::NVPTXTargetMachine32::NVPTXTargetMachine32
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: NVPTXTargetMachine.cpp:139
UseShortPointersOpt
static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)
llvm::initializeNVPTXProxyRegErasurePass
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
llvm::LocalStackSlotAllocationID
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
Definition: LocalStackSlotAllocation.cpp:109
llvm::Optional< Reloc::Model >
llvm::createGVNPass
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3119
llvm::createNVPTXLowerArgsPass
FunctionPass * createNVPTXLowerArgsPass(const NVPTXTargetMachine *TM)
Definition: NVPTXLowerArgs.cpp:379
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:116
STLExtras.h
llvm::StackSlotColoringID
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
Definition: StackSlotColoring.cpp:132
llvm::initializeNVPTXAtomicLowerPass
void initializeNVPTXAtomicLowerPass(PassRegistry &)
llvm::MachineCopyPropagationID
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
Definition: MachineCopyPropagation.cpp:308
NVPTXTargetTransformInfo.h
LegacyPassManager.h
llvm::TwoAddressInstructionPassID
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
Definition: TwoAddressInstructionPass.cpp:194
PassManagerBuilder.h
llvm::createNVPTXAssignValidGlobalNamesPass
ModulePass * createNVPTXAssignValidGlobalNamesPass()
Definition: NVPTXAssignValidGlobalNames.cpp:86
llvm::NVPTXTargetMachine
NVPTXTargetMachine.
Definition: NVPTXTargetMachine.h:25
computeDataLayout
static std::string computeDataLayout(bool is64Bit, bool UseShortPointers)
Definition: NVPTXTargetMachine.cpp:99
F
#define F(x, y, z)
Definition: MD5.cpp:56
NVPTX.h
NVPTXTargetInfo.h
CommandLine.h
llvm::initializeNVPTXLowerAllocaPass
void initializeNVPTXLowerAllocaPass(PassRegistry &)
llvm::LiveDebugValuesID
char & LiveDebugValuesID
LiveDebugValues pass.
Definition: LiveDebugValues.cpp:89
llvm::createInferAddressSpacesPass
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
Definition: InferAddressSpaces.cpp:1299
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
TargetMachine.h
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::NVVMIntrRangePass
Definition: NVPTX.h:51
llvm::PrologEpilogCodeInserterID
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
Definition: PrologEpilogInserter.cpp:139
llvm::createNaryReassociatePass
FunctionPass * createNaryReassociatePass()
Definition: NaryReassociate.cpp:165
llvm::initializeNVPTXLowerAggrCopiesPass
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)
llvm::ADDRESS_SPACE_GLOBAL
@ ADDRESS_SPACE_GLOBAL
Definition: NVPTXBaseInfo.h:23
llvm::FuncletLayoutID
char & FuncletLayoutID
This pass lays out funclets contiguously.
Definition: FuncletLayout.cpp:39
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:94
llvm::createLowerAggrCopies
FunctionPass * createLowerAggrCopies()
NVPTXAtomicLower.h
false
Definition: StackSlotColoring.cpp:142
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
llvm::NVPTXTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: NVPTXTargetMachine.cpp:213
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::ADDRESS_SPACE_CONST
@ ADDRESS_SPACE_CONST
Definition: NVPTXBaseInfo.h:25
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1275
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createNVPTXPrologEpilogPass
MachineFunctionPass * createNVPTXPrologEpilogPass()
Definition: NVPTXPrologEpilogPass.cpp:44
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::NVPTXTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: NVPTXTargetMachine.cpp:200
GVN.h
llvm::createLoadStoreVectorizerPass
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
llvm::StackMapLivenessID
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
Definition: StackMapLivenessAnalysis.cpp:86
llvm::createSpeculativeExecutionPass
FunctionPass * createSpeculativeExecutionPass()
Definition: SpeculativeExecution.cpp:325
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::createNVVMIntrRangePass
FunctionPass * createNVVMIntrRangePass(unsigned int SmVersion)
Definition: NVVMIntrRange.cpp:51
llvm::NVPTX::NVCL
@ NVCL
Definition: NVPTX.h:71
llvm::getTheNVPTXTarget64
Target & getTheNVPTXTarget64()
Definition: NVPTXTargetInfo.cpp:17
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:59
llvm::EarlyTailDuplicateID
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:77
llvm::NVPTXSubtarget
Definition: NVPTXSubtarget.h:31
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::NVPTXTTIImpl
Definition: NVPTXTargetTransformInfo.h:27
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::MachineLoopInfoID
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
Definition: MachineLoopInfo.cpp:44
llvm::cl::opt< bool >
llvm::createModuleToFunctionPassAdaptor
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:1227
llvm::StackColoringID
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
Definition: StackColoring.cpp:551
llvm::NVPTXTargetMachine::NVPTXTargetMachine
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OP, bool is64bit)
Definition: NVPTXTargetMachine.cpp:112
llvm::TargetMachine::setRequiresStructuredCFG
void setRequiresStructuredCFG(bool Value)
Definition: TargetMachine.h:220
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:132
llvm::MachineSinkingID
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
Definition: MachineSink.cpp:256
llvm::ARM_MB::ST
@ ST
Definition: ARMBaseInfo.h:73
move
compiles ldr LCPI1_0 ldr ldr mov lsr tst moveq r1 ldr LCPI1_1 and r0 bx lr It would be better to do something like to fold the shift into the conditional move
Definition: README.txt:546
llvm::Triple::NVCL
@ NVCL
Definition: Triple.h:194
llvm::createNVVMReflectPass
FunctionPass * createNVVMReflectPass(unsigned int SmVersion)
Definition: NVVMReflect.cpp:64
NVPTXAllocaHoisting.h
llvm::NVPTXTargetMachine::getPredicatedAddrSpace
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
Definition: NVPTXTargetMachine.cpp:245
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:844
llvm::createNVPTXAtomicLowerPass
FunctionPass * createNVPTXAtomicLowerPass()
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:441
llvm::ADDRESS_SPACE_SHARED
@ ADDRESS_SPACE_SHARED
Definition: NVPTXBaseInfo.h:24
llvm::LiveVariablesID
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
Definition: LiveVariables.cpp:45
TargetPassConfig.h
llvm::NVPTXTargetObjectFile
Definition: NVPTXTargetObjectFile.h:18
llvm::MachineCSEID
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:153
NVPTXLowerAggrCopies.h
llvm::ProcessImplicitDefsID
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
Definition: ProcessImplicitDefs.cpp:52
llvm::PassBuilder::registerPipelineParsingCallback
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:512
llvm::CodeGenOpt::Aggressive
@ Aggressive
Definition: CodeGen.h:56
llvm::PatchableFunctionID
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
Definition: PatchableFunction.cpp:96
Builder
assume Assume Builder
Definition: AssumeBundleBuilder.cpp:650
Triple.h
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::createNVPTXISelDag
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...
Definition: NVPTXISelDAGToDAG.cpp:33
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:478
llvm::ArrayRef
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: APInt.h:32
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
this
Analysis the ScalarEvolution expression for r is this
Definition: README.txt:8
llvm_unreachable
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Definition: ErrorHandling.h:134
llvm::ShrinkWrapID
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:250
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::initializeNVVMReflectPass
void initializeNVVMReflectPass(PassRegistry &)
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:498
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:41
DisableLoadStoreVectorizer
static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)
llvm::initializeGenericToNVVMPass
void initializeGenericToNVVMPass(PassRegistry &)
llvm::PassManager< Function >
llvm::NVPTXTargetMachine64::NVPTXTargetMachine64
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: NVPTXTargetMachine.cpp:149
std
Definition: BitVector.h:838
llvm::NVPTX::CUDA
@ CUDA
Definition: NVPTX.h:72
llvm::NVVMReflectPass
Definition: NVPTX.h:60
NVPTXTargetMachine.h
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::TailDuplicateID
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
Definition: TailDuplication.cpp:76
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:406
llvm::DeadMachineInstructionElimID
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Definition: DeadMachineInstructionElim.cpp:57
llvm::createNVPTXImageOptimizerPass
FunctionPass * createNVPTXImageOptimizerPass()
Definition: NVPTXImageOptimizer.cpp:176
llvm::MachineSchedulerID
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
Definition: MachineScheduler.cpp:210
DisableRequireStructuredCFG
static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)
llvm::createGenericToNVVMPass
ModulePass * createGenericToNVVMPass()
Definition: NVPTXGenericToNVVM.cpp:64
llvm::PassManagerBuilder::EP_EarlyAsPossible
@ EP_EarlyAsPossible
EP_EarlyAsPossible - This extension point allows adding passes before any other transformations,...
Definition: PassManagerBuilder.h:72
llvm::PostRASchedulerID
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
Definition: PostRASchedulerList.cpp:199
LLVMInitializeNVPTXTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()
Definition: NVPTXTargetMachine.cpp:79
llvm::createStraightLineStrengthReducePass
FunctionPass * createStraightLineStrengthReducePass()
Definition: StraightLineStrengthReduce.cpp:269
NVPTXTargetObjectFile.h
TargetTransformInfo.h
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::initializeNVPTXLowerArgsPass
void initializeNVPTXLowerArgsPass(PassRegistry &)
Vectorize.h
llvm::createNVPTXProxyRegErasurePass
MachineFunctionPass * createNVPTXProxyRegErasurePass()
Definition: NVPTXProxyRegErasure.cpp:119
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:298
llvm::createNVPTXPeephole
MachineFunctionPass * createNVPTXPeephole()
Definition: NVPTXPeephole.cpp:167
llvm::EarlyMachineLICMID
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
Definition: MachineLICM.cpp:298
llvm::NVPTXTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &) override
Allow the target to modify the pass manager, e.g.
Definition: NVPTXTargetMachine.cpp:204
llvm::PostRAMachineSinkingID
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
Definition: MachineSink.cpp:1553
llvm::cl::desc
Definition: CommandLine.h:412
true
basic Basic Alias true
Definition: BasicAliasAnalysis.cpp:1883
llvm::createNVPTXLowerAllocaPass
FunctionPass * createNVPTXLowerAllocaPass()
Definition: NVPTXLowerAlloca.cpp:115
TargetRegistry.h
llvm::createSROAPass
FunctionPass * createSROAPass()
Definition: SROA.cpp:4802
llvm::Value
LLVM Value Representation.
Definition: Value.h:74
llvm::initializeNVPTXAssignValidGlobalNamesPass
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)
PassName
static const char PassName[]
Definition: X86LowerAMXIntrinsics.cpp:670
llvm::initializeNVVMIntrRangePass
void initializeNVVMIntrRangePass(PassRegistry &)
SpecialSubKind::string
@ string
llvm::createAllocaHoisting
FunctionPass * createAllocaHoisting()
llvm::getTheNVPTXTarget32
Target & getTheNVPTXTarget32()
Definition: NVPTXTargetInfo.cpp:13