LLVM 19.0.0git
NVPTXTargetMachine.cpp
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1//===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Top-level implementation for the NVPTX target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXTargetMachine.h"
14#include "NVPTX.h"
15#include "NVPTXAliasAnalysis.h"
16#include "NVPTXAllocaHoisting.h"
17#include "NVPTXAtomicLower.h"
24#include "llvm/ADT/STLExtras.h"
26#include "llvm/CodeGen/Passes.h"
28#include "llvm/IR/IntrinsicsNVPTX.h"
30#include "llvm/Pass.h"
39#include <cassert>
40#include <optional>
41#include <string>
42
43using namespace llvm;
44
45// LSV is still relatively new; this switch lets us turn it off in case we
46// encounter (or suspect) a bug.
47static cl::opt<bool>
48 DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
49 cl::desc("Disable load/store vectorizer"),
50 cl::init(false), cl::Hidden);
51
52// TODO: Remove this flag when we are confident with no regressions.
54 "disable-nvptx-require-structured-cfg",
55 cl::desc("Transitional flag to turn off NVPTX's requirement on preserving "
56 "structured CFG. The requirement should be disabled only when "
57 "unexpected regressions happen."),
58 cl::init(false), cl::Hidden);
59
61 "nvptx-short-ptr",
63 "Use 32-bit pointers for accessing const/local/shared address spaces."),
64 cl::init(false), cl::Hidden);
65
66namespace llvm {
67
83
84} // end namespace llvm
85
87 // Register the target.
90
92 // FIXME: This pass is really intended to be invoked during IR optimization,
93 // but it's very NVPTX-specific.
109}
110
111static std::string computeDataLayout(bool is64Bit, bool UseShortPointers) {
112 std::string Ret = "e";
113
114 if (!is64Bit)
115 Ret += "-p:32:32";
116 else if (UseShortPointers)
117 Ret += "-p3:32:32-p4:32:32-p5:32:32";
118
119 Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
120
121 return Ret;
122}
123
125 StringRef CPU, StringRef FS,
126 const TargetOptions &Options,
127 std::optional<Reloc::Model> RM,
128 std::optional<CodeModel::Model> CM,
129 CodeGenOptLevel OL, bool is64bit)
130 // The pic relocation model is used regardless of what the client has
131 // specified, as it is the only relocation model currently supported.
133 CPU, FS, Options, Reloc::PIC_,
134 getEffectiveCodeModel(CM, CodeModel::Small), OL),
135 is64bit(is64bit), UseShortPointers(UseShortPointersOpt),
136 TLOF(std::make_unique<NVPTXTargetObjectFile>()),
137 Subtarget(TT, std::string(CPU), std::string(FS), *this),
138 StrPool(StrAlloc) {
139 if (TT.getOS() == Triple::NVCL)
140 drvInterface = NVPTX::NVCL;
141 else
142 drvInterface = NVPTX::CUDA;
145 initAsmInfo();
146}
147
149
150void NVPTXTargetMachine32::anchor() {}
151
153 StringRef CPU, StringRef FS,
154 const TargetOptions &Options,
155 std::optional<Reloc::Model> RM,
156 std::optional<CodeModel::Model> CM,
157 CodeGenOptLevel OL, bool JIT)
158 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
159
160void NVPTXTargetMachine64::anchor() {}
161
163 StringRef CPU, StringRef FS,
164 const TargetOptions &Options,
165 std::optional<Reloc::Model> RM,
166 std::optional<CodeModel::Model> CM,
167 CodeGenOptLevel OL, bool JIT)
168 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
169
170namespace {
171
172class NVPTXPassConfig : public TargetPassConfig {
173public:
174 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
175 : TargetPassConfig(TM, PM) {}
176
177 NVPTXTargetMachine &getNVPTXTargetMachine() const {
178 return getTM<NVPTXTargetMachine>();
179 }
180
181 void addIRPasses() override;
182 bool addInstSelector() override;
183 void addPreRegAlloc() override;
184 void addPostRegAlloc() override;
185 void addMachineSSAOptimization() override;
186
187 FunctionPass *createTargetRegisterAllocator(bool) override;
188 void addFastRegAlloc() override;
189 void addOptimizedRegAlloc() override;
190
191 bool addRegAssignAndRewriteFast() override {
192 llvm_unreachable("should not be used");
193 }
194
195 bool addRegAssignAndRewriteOptimized() override {
196 llvm_unreachable("should not be used");
197 }
198
199private:
200 // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
201 // function is only called in opt mode.
202 void addEarlyCSEOrGVNPass();
203
204 // Add passes that propagate special memory spaces.
205 void addAddressSpaceInferencePasses();
206
207 // Add passes that perform straight-line scalar optimizations.
208 void addStraightLineScalarOptimizationPasses();
209};
210
211} // end anonymous namespace
212
214 return new NVPTXPassConfig(*this, PM);
215}
216
218 BumpPtrAllocator &Allocator, const Function &F,
219 const TargetSubtargetInfo *STI) const {
220 return NVPTXMachineFunctionInfo::create<NVPTXMachineFunctionInfo>(Allocator,
221 F, STI);
222}
223
226}
227
229 PassBuilder &PB, bool PopulateClassToPassNames) {
233 if (PassName == "nvvm-reflect") {
235 return true;
236 }
237 if (PassName == "nvvm-intr-range") {
239 return true;
240 }
241 return false;
242 });
243
245 FAM.registerPass([&] { return NVPTXAA(); });
246 });
247
249 if (AAName == "nvptx-aa") {
251 return true;
252 }
253 return false;
254 });
255
259 if (PassName == "nvptx-lower-ctor-dtor") {
261 return true;
262 }
263 if (PassName == "generic-to-nvvm") {
265 return true;
266 }
267 return false;
268 });
269
271 [this](ModulePassManager &PM, OptimizationLevel Level) {
273 FPM.addPass(NVVMReflectPass(Subtarget.getSmVersion()));
274 // FIXME: NVVMIntrRangePass is causing numerical discrepancies,
275 // investigate and re-enable.
276 // FPM.addPass(NVVMIntrRangePass(Subtarget.getSmVersion()));
277 PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
278 });
279}
280
283 return TargetTransformInfo(NVPTXTTIImpl(this, F));
284}
285
286std::pair<const Value *, unsigned>
288 if (auto *II = dyn_cast<IntrinsicInst>(V)) {
289 switch (II->getIntrinsicID()) {
290 case Intrinsic::nvvm_isspacep_const:
291 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_CONST);
292 case Intrinsic::nvvm_isspacep_global:
293 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_GLOBAL);
294 case Intrinsic::nvvm_isspacep_local:
295 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_LOCAL);
296 case Intrinsic::nvvm_isspacep_shared:
297 case Intrinsic::nvvm_isspacep_shared_cluster:
298 return std::make_pair(II->getArgOperand(0), llvm::ADDRESS_SPACE_SHARED);
299 default:
300 break;
301 }
302 }
303 return std::make_pair(nullptr, -1);
304}
305
306void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
307 if (getOptLevel() == CodeGenOptLevel::Aggressive)
308 addPass(createGVNPass());
309 else
310 addPass(createEarlyCSEPass());
311}
312
313void NVPTXPassConfig::addAddressSpaceInferencePasses() {
314 // NVPTXLowerArgs emits alloca for byval parameters which can often
315 // be eliminated by SROA.
316 addPass(createSROAPass());
320}
321
322void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
325 // ReassociateGEPs exposes more opportunites for SLSR. See
326 // the example in reassociate-geps-and-slsr.ll.
328 // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
329 // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
330 // for some of our benchmarks.
331 addEarlyCSEOrGVNPass();
332 // Run NaryReassociate after EarlyCSE/GVN to be more effective.
333 addPass(createNaryReassociatePass());
334 // NaryReassociate on GEPs creates redundant common expressions, so run
335 // EarlyCSE after it.
336 addPass(createEarlyCSEPass());
337}
338
339void NVPTXPassConfig::addIRPasses() {
340 // The following passes are known to not play well with virtual regs hanging
341 // around after register allocation (which in our case, is *all* registers).
342 // We explicitly disable them here. We do, however, need some functionality
343 // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
344 // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
345 disablePass(&PrologEpilogCodeInserterID);
346 disablePass(&MachineLateInstrsCleanupID);
347 disablePass(&MachineCopyPropagationID);
348 disablePass(&TailDuplicateID);
349 disablePass(&StackMapLivenessID);
350 disablePass(&LiveDebugValuesID);
351 disablePass(&PostRAMachineSinkingID);
352 disablePass(&PostRASchedulerID);
353 disablePass(&FuncletLayoutID);
354 disablePass(&PatchableFunctionID);
355 disablePass(&ShrinkWrapID);
356
357 addPass(createNVPTXAAWrapperPass());
358 addPass(createExternalAAWrapperPass([](Pass &P, Function &, AAResults &AAR) {
359 if (auto *WrapperPass = P.getAnalysisIfAvailable<NVPTXAAWrapperPass>())
360 AAR.addAAResult(WrapperPass->getResult());
361 }));
362
363 // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
364 // it here does nothing. But since we need it for correctness when lowering
365 // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
366 // call addEarlyAsPossiblePasses.
367 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
368 addPass(createNVVMReflectPass(ST.getSmVersion()));
369
370 if (getOptLevel() != CodeGenOptLevel::None)
374
375 // NVPTXLowerArgs is required for correctness and should be run right
376 // before the address space inference passes.
377 addPass(createNVPTXLowerArgsPass());
378 if (getOptLevel() != CodeGenOptLevel::None) {
379 addAddressSpaceInferencePasses();
380 addStraightLineScalarOptimizationPasses();
381 }
382
383 addPass(createAtomicExpandPass());
385
386 // === LSR and other generic IR passes ===
388 // EarlyCSE is not always strong enough to clean up what LSR produces. For
389 // example, GVN can combine
390 //
391 // %0 = add %a, %b
392 // %1 = add %b, %a
393 //
394 // and
395 //
396 // %0 = shl nsw %a, 2
397 // %1 = shl %a, 2
398 //
399 // but EarlyCSE can do neither of them.
400 if (getOptLevel() != CodeGenOptLevel::None) {
401 addEarlyCSEOrGVNPass();
404 addPass(createSROAPass());
405 }
406
407 const auto &Options = getNVPTXTargetMachine().Options;
408 addPass(createNVPTXLowerUnreachablePass(Options.TrapUnreachable,
409 Options.NoTrapAfterNoreturn));
410}
411
412bool NVPTXPassConfig::addInstSelector() {
413 const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
414
415 addPass(createLowerAggrCopies());
416 addPass(createAllocaHoisting());
417 addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
418
419 if (!ST.hasImageHandles())
421
422 return false;
423}
424
425void NVPTXPassConfig::addPreRegAlloc() {
426 // Remove Proxy Register pseudo instructions used to keep `callseq_end` alive.
428}
429
430void NVPTXPassConfig::addPostRegAlloc() {
432 if (getOptLevel() != CodeGenOptLevel::None) {
433 // NVPTXPrologEpilogPass calculates frame object offset and replace frame
434 // index with VRFrame register. NVPTXPeephole need to be run after that and
435 // will replace VRFrame with VRFrameLocal when possible.
436 addPass(createNVPTXPeephole());
437 }
438}
439
440FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
441 return nullptr; // No reg alloc
442}
443
444void NVPTXPassConfig::addFastRegAlloc() {
445 addPass(&PHIEliminationID);
447}
448
449void NVPTXPassConfig::addOptimizedRegAlloc() {
450 addPass(&ProcessImplicitDefsID);
451 addPass(&LiveVariablesID);
452 addPass(&MachineLoopInfoID);
453 addPass(&PHIEliminationID);
454
456 addPass(&RegisterCoalescerID);
457
458 // PreRA instruction scheduling.
459 if (addPass(&MachineSchedulerID))
460 printAndVerify("After Machine Scheduling");
461
462 addPass(&StackSlotColoringID);
463
464 // FIXME: Needs physical registers
465 // addPass(&MachineLICMID);
466
467 printAndVerify("After StackSlotColoring");
468}
469
470void NVPTXPassConfig::addMachineSSAOptimization() {
471 // Pre-ra tail duplication.
472 if (addPass(&EarlyTailDuplicateID))
473 printAndVerify("After Pre-RegAlloc TailDuplicate");
474
475 // Optimize PHIs before DCE: removing dead PHI cycles may make more
476 // instructions dead.
477 addPass(&OptimizePHIsID);
478
479 // This pass merges large allocas. StackSlotColoring is a different pass
480 // which merges spill slots.
481 addPass(&StackColoringID);
482
483 // If the target requests it, assign local variables to stack slots relative
484 // to one another and simplify frame index references where possible.
486
487 // With optimization, dead code should already be eliminated. However
488 // there is one known exception: lowered code for arguments that are only
489 // used by tail calls, where the tail calls reuse the incoming stack
490 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
492 printAndVerify("After codegen DCE pass");
493
494 // Allow targets to insert passes that improve instruction level parallelism,
495 // like if-conversion. Such passes will typically need dominator trees and
496 // loop info, just like LICM and CSE below.
497 if (addILPOpts())
498 printAndVerify("After ILP optimizations");
499
500 addPass(&EarlyMachineLICMID);
501 addPass(&MachineCSEID);
502
503 addPass(&MachineSinkingID);
504 printAndVerify("After Machine LICM, CSE and Sinking passes");
505
506 addPass(&PeepholeOptimizerID);
507 printAndVerify("After codegen peephole optimization pass");
508}
basic Basic Alias true
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file provides the interface for LLVM's Global Value Numbering pass which eliminates fully redund...
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
This is the NVPTX address space based alias analysis pass.
static cl::opt< bool > DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer", cl::desc("Disable load/store vectorizer"), cl::init(false), cl::Hidden)
static cl::opt< bool > DisableRequireStructuredCFG("disable-nvptx-require-structured-cfg", cl::desc("Transitional flag to turn off NVPTX's requirement on preserving " "structured CFG. The requirement should be disabled only when " "unexpected regressions happen."), cl::init(false), cl::Hidden)
static cl::opt< bool > UseShortPointersOpt("nvptx-short-ptr", cl::desc("Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget()
This file a TargetTransformInfo::Concept conforming object specific to the NVPTX target machine.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define P(N)
FunctionAnalysisManager FAM
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
Basic Register Allocator
This file contains some templates that are useful if you are working with the STL at all.
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static bool is64Bit(const char *name)
static const char PassName[]
A manager for alias analyses.
void registerFunctionAnalysis()
Register a specific AA result.
void addAAResult(AAResultT &AAResult)
Register a specific AA result.
A container for analyses that lazily runs them and caches their results.
Definition: PassManager.h:348
bool registerPass(PassBuilderT &&PassBuilder)
Register an analysis pass with the manager.
Definition: PassManager.h:562
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Legacy wrapper pass to provide the NVPTXAAResult object.
Analysis pass providing a never-invalidated alias analysis result.
Lower llvm.global_ctors and llvm.global_dtors to special kernels.
unsigned int getSmVersion() const
NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
void registerDefaultAliasAnalyses(AAManager &AAM) override
Allow the target to register alias analyses with the AAManager for use with the new pass manager.
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const override
If the specified predicate checks whether a generic pointer falls within a specified address space,...
~NVPTXTargetMachine() override
NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OP, bool is64bit)
void registerPassBuilderCallbacks(PassBuilder &PB, bool PopulateClassToPassNames) override
Allow the target to modify the pass pipeline.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:104
void registerPipelineStartEPCallback(const std::function< void(ModulePassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:466
void registerParseAACallback(const std::function< bool(StringRef Name, AAManager &AA)> &C)
Register a callback for parsing an AliasAnalysis Name to populate the given AAManager AA.
Definition: PassBuilder.h:518
void registerAnalysisRegistrationCallback(const std::function< void(CGSCCAnalysisManager &)> &C)
{{@ Register callbacks for analysis registration with this PassBuilder instance.
Definition: PassBuilder.h:526
void registerPipelineParsingCallback(const std::function< bool(StringRef Name, CGSCCPassManager &, ArrayRef< PipelineElement >)> &C)
{{@ Register pipeline parsing callbacks with this pass builder instance.
Definition: PassBuilder.h:552
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t<!std::is_same< PassT, PassManager >::value > addPass(PassT &&Pass)
Definition: PassManager.h:273
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
void setRequiresStructuredCFG(bool Value)
std::unique_ptr< const MCSubtargetInfo > STI
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ NVCL
Definition: NVPTX.h:79
@ CUDA
Definition: NVPTX.h:80
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void initializeNVPTXLowerAllocaPass(PassRegistry &)
char & EarlyMachineLICMID
This pass performs loop invariant code motion on machine instructions.
ModulePass * createNVPTXAssignValidGlobalNamesPass()
MachineFunctionPass * createNVPTXReplaceImageHandlesPass()
FunctionPass * createNVPTXLowerUnreachablePass(bool TrapUnreachable, bool NoTrapAfterNoreturn)
void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &)
Pass * createLoadStoreVectorizerPass()
Create a legacy pass manager instance of the LoadStoreVectorizer pass.
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
char & OptimizePHIsID
OptimizePHIs - This pass optimizes machine instruction PHIs to take advantage of opportunities create...
char & EarlyTailDuplicateID
Duplicate blocks with unconditional branches into tails of their predecessors.
ModuleToFunctionPassAdaptor createModuleToFunctionPassAdaptor(FunctionPassT &&Pass, bool EagerlyInvalidate=false)
A function to deduce a function pass type and wrap it in the templated adaptor.
Definition: PassManager.h:943
ModulePass * createGenericToNVVMLegacyPass()
FunctionPass * createNVVMReflectPass(unsigned int SmVersion)
Definition: NVVMReflect.cpp:68
void initializeNVPTXLowerAggrCopiesPass(PassRegistry &)
void initializeNVPTXExternalAAWrapperPass(PassRegistry &)
char & MachineSinkingID
MachineSinking - This pass performs sinking on machine instructions.
@ ADDRESS_SPACE_LOCAL
Definition: NVPTXBaseInfo.h:26
@ ADDRESS_SPACE_CONST
Definition: NVPTXBaseInfo.h:25
@ ADDRESS_SPACE_GLOBAL
Definition: NVPTXBaseInfo.h:23
@ ADDRESS_SPACE_SHARED
Definition: NVPTXBaseInfo.h:24
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
MachineFunctionPass * createNVPTXPrologEpilogPass()
MachineFunctionPass * createNVPTXProxyRegErasurePass()
void initializeNVPTXDAGToDAGISelPass(PassRegistry &)
char & TailDuplicateID
TailDuplicate - Duplicate blocks with unconditional branches into tails of their predecessors.
FunctionPass * createNaryReassociatePass()
char & PatchableFunctionID
This pass implements the "patchable-function" attribute.
char & PostRASchedulerID
PostRAScheduler - This pass performs post register allocation scheduling.
MachineFunctionPass * createNVPTXPeephole()
void initializeNVVMReflectPass(PassRegistry &)
char & MachineSchedulerID
MachineScheduler - This pass schedules machine instructions.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
char & LiveDebugValuesID
LiveDebugValues pass.
FunctionPass * createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOptLevel OptLevel)
createNVPTXISelDag - This pass converts a legalized DAG into a NVPTX-specific DAG,...
char & PrologEpilogCodeInserterID
PrologEpilogCodeInserter - This pass inserts prolog and epilog code, and eliminates abstract frame re...
void initializeGenericToNVVMLegacyPassPass(PassRegistry &)
void initializeNVPTXCtorDtorLoweringLegacyPass(PassRegistry &)
void initializeNVPTXLowerUnreachablePass(PassRegistry &)
void initializeNVPTXLowerArgsPass(PassRegistry &)
char & MachineLoopInfoID
MachineLoopInfo - This pass is a loop analysis pass.
FunctionPass * createNVPTXLowerArgsPass()
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
char & ShrinkWrapID
ShrinkWrap pass. Look for the best place to insert save and restore.
Definition: ShrinkWrap.cpp:286
char & MachineLateInstrsCleanupID
MachineLateInstrsCleanup - This pass removes redundant identical instructions after register allocati...
void initializeNVPTXAAWrapperPassPass(PassRegistry &)
FunctionPass * createNVPTXImageOptimizerPass()
FunctionPass * createNVPTXLowerAllocaPass()
FunctionPass * createSpeculativeExecutionPass()
char & StackMapLivenessID
StackMapLiveness - This pass analyses the register live-out set of stackmap/patchpoint intrinsics and...
char & FuncletLayoutID
This pass lays out funclets contiguously.
FunctionPass * createAllocaHoisting()
void initializeNVVMIntrRangePass(PassRegistry &)
char & StackColoringID
StackSlotColoring - This pass performs stack coloring and merging.
char & PostRAMachineSinkingID
This pass perform post-ra machine sink for COPY instructions.
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
char & StackSlotColoringID
StackSlotColoring - This pass performs stack slot coloring.
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
FunctionPass * createLowerAggrCopies()
char & ProcessImplicitDefsID
ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
char & MachineCSEID
MachineCSE - This pass performs global CSE on machine instructions.
Definition: MachineCSE.cpp:165
FunctionPass * createNVPTXAtomicLowerPass()
ModulePass * createNVPTXCtorDtorLoweringLegacyPass()
char & LiveVariablesID
LiveVariables pass - This pass computes the set of blocks in which each variable is life and sets mac...
FunctionPass * createGVNPass(bool NoMemDepAnalysis=false)
Create a legacy GVN pass.
Definition: GVN.cpp:3336
void initializeNVPTXAllocaHoistingPass(PassRegistry &)
Target & getTheNVPTXTarget64()
FunctionPass * createInferAddressSpacesPass(unsigned AddressSpace=~0u)
void initializeNVPTXProxyRegErasurePass(PassRegistry &)
ImmutablePass * createNVPTXAAWrapperPass()
ImmutablePass * createExternalAAWrapperPass(std::function< void(Pass &, Function &, AAResults &)> Callback)
A wrapper pass around a callback which can be used to populate the AAResults in the AAResultsWrapperP...
char & TwoAddressInstructionPassID
TwoAddressInstruction - This pass reduces two-address instructions to use two operands.
char & LocalStackSlotAllocationID
LocalStackSlotAllocation - This pass assigns local frame indices to stack slots relative to one anoth...
FunctionPass * createStraightLineStrengthReducePass()
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1932
char & PHIEliminationID
PHIElimination - This pass eliminates machine instruction PHI nodes by inserting copy instructions.
FunctionPass * createSROAPass(bool PreserveCFG=true)
Definition: SROA.cpp:5466
void initializeNVPTXAtomicLowerPass(PassRegistry &)
char & MachineCopyPropagationID
MachineCopyPropagation - This pass performs copy propagation on machine instructions.
char & DeadMachineInstructionElimID
DeadMachineInstructionElim - This pass removes dead machine instructions.
Target & getTheNVPTXTarget32()
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
RegisterTargetMachine - Helper template for registering a target machine implementation,...