LLVM 19.0.0git
HexagonTargetMachine.cpp
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1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
23#include "llvm/CodeGen/Passes.h"
26#include "llvm/IR/Module.h"
31#include <optional>
32
33using namespace llvm;
34
35static cl::opt<bool>
36 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37 cl::desc("Enable Hexagon constant-extender optimization"));
38
40 cl::desc("Enable RDF-based optimizations"));
41
43 "rdf-bb-limit", cl::Hidden, cl::init(1000),
44 cl::desc("Basic block limit for a function for RDF optimizations"));
45
46static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
47 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
48
49static cl::opt<bool>
50 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
51 cl::desc("Disable Hexagon Addressing Mode Optimization"));
52
53static cl::opt<bool>
54 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
55 cl::desc("Disable Hexagon CFG Optimization"));
56
57static cl::opt<bool>
58 DisableHCP("disable-hcp", cl::Hidden,
59 cl::desc("Disable Hexagon constant propagation"));
60
61static cl::opt<bool> DisableStoreWidening("disable-store-widen",
62 cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
63
64static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
65 cl::init(true), cl::Hidden,
66 cl::desc("Early expansion of MUX"));
67
68static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
69 cl::desc("Enable early if-conversion"));
70
71static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
72 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
73
74static cl::opt<bool>
75 EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
76 cl::desc("Enable commoning of GEP instructions"));
77
78static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
79 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
80
81static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
82 cl::desc("Enable converting conditional transfers into MUX instructions"));
83
84static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
85 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
86 "predicate instructions"));
87
88static cl::opt<bool>
89 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
90 cl::desc("Enable loop data prefetch on Hexagon"));
91
92static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
93 cl::desc("Disable splitting double registers"));
94
95static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
96 cl::Hidden, cl::desc("Bit simplification"));
97
98static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
99 cl::Hidden, cl::desc("Loop rescheduling"));
100
101static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
102 cl::Hidden, cl::desc("Disable backend optimizations"));
103
104static cl::opt<bool>
105 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
106 cl::desc("Enable Hexagon Vector print instr pass"));
107
108static cl::opt<bool>
109 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
110 cl::desc("Enable vextract optimization"));
111
112static cl::opt<bool>
113 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
114 cl::desc("Enable HVX vector combining"));
115
117 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
118 cl::desc("Simplify the CFG after atomic expansion pass"));
119
120static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
121 cl::init(true),
122 cl::desc("Enable instsimplify"));
123
125 "hexagon-postinc-opt", cl::Hidden,
126 cl::desc("Disable Hexagon post-increment optimization"));
127
128/// HexagonTargetMachineModule - Note that this is used on hosts that
129/// cannot link in a library unless there are references into the
130/// library. In particular, it seems that it is not possible to get
131/// things to work on Win32 without this. Though it is unused, do not
132/// remove it.
135
138 C, std::make_unique<HexagonConvergingVLIWScheduler>());
139 DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
140 DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
141 DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
143 return DAG;
144}
145
147SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
149
150namespace llvm {
151 extern char &HexagonExpandCondsetsID;
172
189 CodeGenOptLevel OptLevel);
204} // end namespace llvm;
205
206static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
207 return RM.value_or(Reloc::Static);
208}
209
211 // Register the target.
213
233}
234
236 StringRef CPU, StringRef FS,
237 const TargetOptions &Options,
238 std::optional<Reloc::Model> RM,
239 std::optional<CodeModel::Model> CM,
240 CodeGenOptLevel OL, bool JIT)
241 // Specify the vector alignment explicitly. For v512x1, the calculated
242 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
243 // the required minimum of 64 bytes.
245 T,
246 "e-m:e-p:32:32:32-a:0-n16:32-"
247 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
248 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
249 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
250 getEffectiveCodeModel(CM, CodeModel::Small),
252 TLOF(std::make_unique<HexagonTargetObjectFile>()) {
255 initAsmInfo();
256}
257
258const HexagonSubtarget *
260 AttributeList FnAttrs = F.getAttributes();
261 Attribute CPUAttr =
262 FnAttrs.getFnAttr("target-cpu");
263 Attribute FSAttr =
264 FnAttrs.getFnAttr("target-features");
265
266 std::string CPU =
267 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
268 std::string FS =
269 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
270 // Append the preexisting target features last, so that +mattr overrides
271 // the "unsafe-fp-math" function attribute.
272 // Creating a separate target feature is not strictly necessary, it only
273 // exists to make "unsafe-fp-math" force creating a new subtarget.
274
275 if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
276 FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
277
278 auto &I = SubtargetMap[CPU + FS];
279 if (!I) {
280 // This needs to be done before we create a new subtarget since any
281 // creation will depend on the TM and the code generation flags on the
282 // function that reside in TargetOptions.
284 I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
285 }
286 return I.get();
287}
288
290 PassBuilder &PB, bool PopulateClassToPassNames) {
292 [=](LoopPassManager &LPM, OptimizationLevel Level) {
294 });
296 [=](LoopPassManager &LPM, OptimizationLevel Level) {
298 });
299}
300
303 return TargetTransformInfo(HexagonTTIImpl(this, F));
304}
305
307 BumpPtrAllocator &Allocator, const Function &F,
308 const TargetSubtargetInfo *STI) const {
309 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
310 Allocator, F, STI);
311}
312
314
315namespace {
316/// Hexagon Code Generator Pass Configuration Options.
317class HexagonPassConfig : public TargetPassConfig {
318public:
319 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
320 : TargetPassConfig(TM, PM) {}
321
322 HexagonTargetMachine &getHexagonTargetMachine() const {
323 return getTM<HexagonTargetMachine>();
324 }
325
327 createMachineScheduler(MachineSchedContext *C) const override {
329 }
330
331 void addIRPasses() override;
332 bool addInstSelector() override;
333 void addPreRegAlloc() override;
334 void addPostRegAlloc() override;
335 void addPreSched2() override;
336 void addPreEmitPass() override;
337};
338} // namespace
339
341 return new HexagonPassConfig(*this, PM);
342}
343
344void HexagonPassConfig::addIRPasses() {
346 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
347
348 if (!NoOpt) {
352 }
353
354 addPass(createAtomicExpandPass());
355
356 if (!NoOpt) {
359 .forwardSwitchCondToPhi(true)
360 .convertSwitchRangeToICmp(true)
361 .convertSwitchToLookupTable(true)
362 .needCanonicalLoops(false)
363 .hoistCommonInsts(true)
364 .sinkCommonInsts(true)));
369 if (EnableCommGEP)
370 addPass(createHexagonCommonGEP());
371 // Replace certain combinations of shifts and ands with extracts.
373 addPass(createHexagonGenExtract());
374 }
375}
376
377bool HexagonPassConfig::addInstSelector() {
378 HexagonTargetMachine &TM = getHexagonTargetMachine();
379 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
380
381 if (!NoOpt)
383
384 addPass(createHexagonISelDag(TM, getOptLevel()));
385
386 if (!NoOpt) {
388 addPass(createHexagonVExtract());
389 // Create logical operations on predicate registers.
390 if (EnableGenPred)
391 addPass(createHexagonGenPredicate());
392 // Rotate loops to expose bit-simplification opportunities.
395 // Split double registers.
396 if (!DisableHSDR)
398 // Bit simplification.
400 addPass(createHexagonBitSimplify());
401 addPass(createHexagonPeephole());
402 // Constant propagation.
403 if (!DisableHCP) {
406 }
407 if (EnableGenInsert)
408 addPass(createHexagonGenInsert());
409 if (EnableEarlyIf)
411 }
412
413 return false;
414}
415
416void HexagonPassConfig::addPreRegAlloc() {
417 if (getOptLevel() != CodeGenOptLevel::None) {
418 if (EnableCExtOpt)
426 }
427
428 if (TM->getOptLevel() >= CodeGenOptLevel::Aggressive)
430 addPass(createHexagonPostIncOpt());
431
432 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
433 addPass(&MachinePipelinerID);
434}
435
436void HexagonPassConfig::addPostRegAlloc() {
437 if (getOptLevel() != CodeGenOptLevel::None) {
438 if (EnableRDFOpt)
439 addPass(createHexagonRDFOpt());
441 addPass(createHexagonCFGOptimizer());
442 if (!DisableAModeOpt)
443 addPass(createHexagonOptAddrMode());
444 }
445}
446
447void HexagonPassConfig::addPreSched2() {
449 if (getOptLevel() != CodeGenOptLevel::None)
450 addPass(&IfConverterID);
452}
453
454void HexagonPassConfig::addPreEmitPass() {
455 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
456
457 if (!NoOpt)
458 addPass(createHexagonNewValueJump());
459
461
462 if (!NoOpt) {
464 addPass(createHexagonFixupHwLoops());
465 // Generate MUX from pairs of conditional transfers.
466 if (EnableGenMux)
467 addPass(createHexagonGenMux());
468 }
469
470 // Packetization is mandatory: it handles gather/scatter at all opt levels.
471 addPass(createHexagonPacketizer(NoOpt));
472
474 addPass(createHexagonVectorPrint());
475
476 // Add CFI instructions if necessary.
478}
static cl::opt< bool > EnableLoopPrefetch("amdgpu-loop-prefetch", cl::desc("Enable loop data prefetch on AMDGPU"), cl::Hidden, cl::init(false))
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))
static cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))
static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
static cl::opt< bool > DisableHexagonPostIncOpt("hexagon-postinc-opt", cl::Hidden, cl::desc("Disable Hexagon post-increment optimization"))
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
cl::opt< unsigned > RDFFuncBlockLimit("rdf-bb-limit", cl::Hidden, cl::init(1000), cl::desc("Basic block limit for a function for RDF optimizations"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine.
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Module.h This file contains the declarations for the Module class.
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
Basic Register Allocator
Target-Independent Code Generator Pass Configuration Options pass.
@ None
Attribute getFnAttr(Attribute::AttrKind Kind) const
Return the attribute object that exists for the function.
Definition: Attributes.h:826
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
void registerPassBuilderCallbacks(PassBuilder &PB, bool PopulateClassToPassNames) override
Allow the target to modify the pass pipeline.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
MachineSchedRegistry provides a selection of available machine instruction schedulers.
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:104
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:413
void registerLoopOptimizerEndEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:423
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:557
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:558
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createHexagonVectorPrint()
FunctionPass * createHexagonVectorCombineLegacyPass()
void initializeHexagonOptAddrModePass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
FunctionPass * createHexagonPostIncOpt()
void initializeHexagonNewValueJumpPass(PassRegistry &)
FunctionPass * createHexagonCFGOptimizer()
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
void initializeHexagonPostIncOptPass(PassRegistry &)
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:145
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
Pass * createHexagonLoopIdiomPass()
FunctionPass * createHexagonNewValueJump()
void initializeHexagonRDFOptPass(PassRegistry &)
FunctionPass * createHexagonBranchRelaxation()
FunctionPass * createHexagonBitSimplify()
FunctionPass * createHexagonPeephole()
FunctionPass * createHexagonConstExtenders()
FunctionPass * createHexagonConstPropagationPass()
FunctionPass * createHexagonFixupHwLoops()
void initializeHexagonDAGToDAGISelPass(PassRegistry &)
Target & getTheHexagonTarget()
void initializeHexagonExpandCondsetsPass(PassRegistry &)
void initializeHexagonPacketizerPass(PassRegistry &)
FunctionPass * createHexagonPacketizer(bool Minimal)
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonEarlyIfConversion()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCallFrameInformation()
FunctionPass * createHexagonVExtract()
FunctionPass * createHexagonGenPredicate()
void initializeHexagonVectorCombineLegacyPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createHexagonGenInsert()
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createHexagonLoopRescheduling()
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
FunctionPass * createHexagonSplitConst32AndConst64()
FunctionPass * createHexagonCopyToCombine()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
FunctionPass * createHexagonCommonGEP()
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel)
createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...
char & HexagonExpandCondsetsID
FunctionPass * createHexagonOptAddrMode()
void initializeHexagonCopyToCombinePass(PassRegistry &)
void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonHardwareLoops()
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Pass * createHexagonVectorLoopCarriedReuseLegacyPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
void initializeHexagonConstExtendersPass(PassRegistry &)
FunctionPass * createHexagonStoreWidening()
void initializeHexagonGenMuxPass(PassRegistry &Registry)
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
void initializeHexagonHardwareLoopsPass(PassRegistry &)
FunctionPass * createHexagonRDFOpt()
FunctionPass * createInstSimplifyLegacyPass()
void initializeHexagonVExtractPass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
Hexagon Vector Loop Carried Reuse Pass.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...