LLVM 19.0.0git
HexagonTargetMachine.cpp
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1//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Implements the info about Hexagon target spec.
10//
11//===----------------------------------------------------------------------===//
12
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
23#include "llvm/CodeGen/Passes.h"
26#include "llvm/IR/Module.h"
31#include <optional>
32
33using namespace llvm;
34
35static cl::opt<bool>
36 EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37 cl::desc("Enable Hexagon constant-extender optimization"));
38
40 cl::desc("Enable RDF-based optimizations"));
41
43 "rdf-bb-limit", cl::Hidden, cl::init(1000),
44 cl::desc("Basic block limit for a function for RDF optimizations"));
45
46static cl::opt<bool>
47 DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden,
48 cl::desc("Disable Hardware Loops for Hexagon target"));
49
50static cl::opt<bool>
51 DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
52 cl::desc("Disable Hexagon Addressing Mode Optimization"));
53
54static cl::opt<bool>
55 DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
56 cl::desc("Disable Hexagon CFG Optimization"));
57
58static cl::opt<bool>
59 DisableHCP("disable-hcp", cl::Hidden,
60 cl::desc("Disable Hexagon constant propagation"));
61
62static cl::opt<bool> DisableStoreWidening("disable-store-widen", cl::Hidden,
63 cl::init(false),
64 cl::desc("Disable store widening"));
65
66static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
67 cl::init(true), cl::Hidden,
68 cl::desc("Early expansion of MUX"));
69
70static cl::opt<bool> EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true),
72 cl::desc("Cleanup of TFRs/COPYs"));
73
74static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
75 cl::desc("Enable early if-conversion"));
76
77static cl::opt<bool> EnableCopyHoist("hexagon-copy-hoist", cl::init(true),
79 cl::desc("Enable Hexagon copy hoisting"));
80
81static cl::opt<bool>
82 EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden,
83 cl::desc("Generate \"insert\" instructions"));
84
85static cl::opt<bool>
86 EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
87 cl::desc("Enable commoning of GEP instructions"));
88
89static cl::opt<bool>
90 EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden,
91 cl::desc("Generate \"extract\" instructions"));
92
94 "hexagon-mux", cl::init(true), cl::Hidden,
95 cl::desc("Enable converting conditional transfers into MUX instructions"));
96
97static cl::opt<bool>
98 EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden,
99 cl::desc("Enable conversion of arithmetic operations to "
100 "predicate instructions"));
101
102static cl::opt<bool>
103 EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
104 cl::desc("Enable loop data prefetch on Hexagon"));
105
106static cl::opt<bool>
107 DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
108 cl::desc("Disable splitting double registers"));
109
110static cl::opt<bool>
111 EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden,
112 cl::desc("Generate absolute set instructions"));
113
114static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
116 cl::desc("Bit simplification"));
117
118static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
120 cl::desc("Loop rescheduling"));
121
122static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden,
123 cl::desc("Disable backend optimizations"));
124
125static cl::opt<bool>
126 EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
127 cl::desc("Enable Hexagon Vector print instr pass"));
128
129static cl::opt<bool>
130 EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
131 cl::desc("Enable vextract optimization"));
132
133static cl::opt<bool>
134 EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
135 cl::desc("Enable HVX vector combining"));
136
138 "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
139 cl::desc("Simplify the CFG after atomic expansion pass"));
140
141static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
142 cl::init(true),
143 cl::desc("Enable instsimplify"));
144
145/// HexagonTargetMachineModule - Note that this is used on hosts that
146/// cannot link in a library unless there are references into the
147/// library. In particular, it seems that it is not possible to get
148/// things to work on Win32 without this. Though it is unused, do not
149/// remove it.
152
155 C, std::make_unique<HexagonConvergingVLIWScheduler>());
156 DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
157 DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
158 DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
160 return DAG;
161}
162
164 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
166
167namespace llvm {
168extern char &HexagonCopyHoistingID;
169extern char &HexagonExpandCondsetsID;
170extern char &HexagonTfrCleanupID;
194
213 CodeGenOptLevel OptLevel);
229} // namespace llvm
230
231static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
232 return RM.value_or(Reloc::Static);
233}
234
236 // Register the target.
238
258}
259
261 StringRef CPU, StringRef FS,
262 const TargetOptions &Options,
263 std::optional<Reloc::Model> RM,
264 std::optional<CodeModel::Model> CM,
265 CodeGenOptLevel OL, bool JIT)
266 // Specify the vector alignment explicitly. For v512x1, the calculated
267 // alignment would be 512*alignment(i1), which is 512 bytes, instead of
268 // the required minimum of 64 bytes.
270 T,
271 "e-m:e-p:32:32:32-a:0-n16:32-"
272 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
273 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
274 TT, CPU, FS, Options, getEffectiveRelocModel(RM),
275 getEffectiveCodeModel(CM, CodeModel::Small),
277 TLOF(std::make_unique<HexagonTargetObjectFile>()),
278 Subtarget(Triple(TT), CPU, FS, *this) {
283 initAsmInfo();
284}
285
286const HexagonSubtarget *
288 AttributeList FnAttrs = F.getAttributes();
289 Attribute CPUAttr = FnAttrs.getFnAttr("target-cpu");
290 Attribute FSAttr = FnAttrs.getFnAttr("target-features");
291
292 std::string CPU =
293 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
294 std::string FS =
295 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
296 // Append the preexisting target features last, so that +mattr overrides
297 // the "unsafe-fp-math" function attribute.
298 // Creating a separate target feature is not strictly necessary, it only
299 // exists to make "unsafe-fp-math" force creating a new subtarget.
300
301 if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
302 FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
303
304 auto &I = SubtargetMap[CPU + FS];
305 if (!I) {
306 // This needs to be done before we create a new subtarget since any
307 // creation will depend on the TM and the code generation flags on the
308 // function that reside in TargetOptions.
310 I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
311 }
312 return I.get();
313}
314
316 PassBuilder &PB, bool PopulateClassToPassNames) {
317#define GET_PASS_REGISTRY "HexagonPassRegistry.def"
319
321 [=](LoopPassManager &LPM, OptimizationLevel Level) {
323 });
325 [=](LoopPassManager &LPM, OptimizationLevel Level) {
327 });
328}
329
332 return TargetTransformInfo(HexagonTTIImpl(this, F));
333}
334
336 BumpPtrAllocator &Allocator, const Function &F,
337 const TargetSubtargetInfo *STI) const {
338 return HexagonMachineFunctionInfo::create<HexagonMachineFunctionInfo>(
339 Allocator, F, STI);
340}
341
343
344namespace {
345/// Hexagon Code Generator Pass Configuration Options.
346class HexagonPassConfig : public TargetPassConfig {
347public:
348 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
349 : TargetPassConfig(TM, PM) {}
350
351 HexagonTargetMachine &getHexagonTargetMachine() const {
352 return getTM<HexagonTargetMachine>();
353 }
354
356 createMachineScheduler(MachineSchedContext *C) const override {
358 }
359
360 void addIRPasses() override;
361 bool addInstSelector() override;
362 void addPreRegAlloc() override;
363 void addPostRegAlloc() override;
364 void addPreSched2() override;
365 void addPreEmitPass() override;
366};
367} // namespace
368
370 return new HexagonPassConfig(*this, PM);
371}
372
373void HexagonPassConfig::addIRPasses() {
375 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
376
377 if (!NoOpt) {
381 }
382
384
385 if (!NoOpt) {
388 .forwardSwitchCondToPhi(true)
389 .convertSwitchRangeToICmp(true)
390 .convertSwitchToLookupTable(true)
391 .needCanonicalLoops(false)
392 .hoistCommonInsts(true)
393 .sinkCommonInsts(true)));
398 if (EnableCommGEP)
399 addPass(createHexagonCommonGEP());
400 // Replace certain combinations of shifts and ands with extracts.
402 addPass(createHexagonGenExtract());
403 }
404}
405
406bool HexagonPassConfig::addInstSelector() {
407 HexagonTargetMachine &TM = getHexagonTargetMachine();
408 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
409
410 if (!NoOpt)
412
413 addPass(createHexagonISelDag(TM, getOptLevel()));
414
415 if (!NoOpt) {
417 addPass(createHexagonVExtract());
418 // Create logical operations on predicate registers.
419 if (EnableGenPred)
420 addPass(createHexagonGenPredicate());
421 // Rotate loops to expose bit-simplification opportunities.
424 // Split double registers.
425 if (!DisableHSDR)
427 // Bit simplification.
429 addPass(createHexagonBitSimplify());
430 addPass(createHexagonPeephole());
431 // Constant propagation.
432 if (!DisableHCP) {
435 }
436 if (EnableGenInsert)
437 addPass(createHexagonGenInsert());
438 if (EnableEarlyIf)
440 }
441
442 return false;
443}
444
445void HexagonPassConfig::addPreRegAlloc() {
446 if (getOptLevel() != CodeGenOptLevel::None) {
447 if (EnableCExtOpt)
451 if (EnableCopyHoist)
457 if (EnableGenMemAbs)
461 }
462 if (TM->getOptLevel() >= CodeGenOptLevel::Default)
463 addPass(&MachinePipelinerID);
464}
465
466void HexagonPassConfig::addPostRegAlloc() {
467 if (getOptLevel() != CodeGenOptLevel::None) {
468 if (EnableRDFOpt)
469 addPass(createHexagonRDFOpt());
471 addPass(createHexagonCFGOptimizer());
472 if (!DisableAModeOpt)
473 addPass(createHexagonOptAddrMode());
474 }
475}
476
477void HexagonPassConfig::addPreSched2() {
479 if (getOptLevel() != CodeGenOptLevel::None)
480 addPass(&IfConverterID);
482}
483
484void HexagonPassConfig::addPreEmitPass() {
485 bool NoOpt = (getOptLevel() == CodeGenOptLevel::None);
486
487 if (!NoOpt)
488 addPass(createHexagonNewValueJump());
489
491
492 if (!NoOpt) {
494 addPass(createHexagonFixupHwLoops());
495 // Generate MUX from pairs of conditional transfers.
496 if (EnableGenMux)
497 addPass(createHexagonGenMux());
498 }
499
500 // Packetization is mandatory: it handles gather/scatter at all opt levels.
501 addPass(createHexagonPacketizer(NoOpt));
502
503 if (!NoOpt)
504 addPass(createHexagonLoopAlign());
505
507 addPass(createHexagonVectorPrint());
508
509 // Add CFI instructions if necessary.
511}
static cl::opt< bool > EnableLoopPrefetch("amdgpu-loop-prefetch", cl::desc("Enable loop data prefetch on AMDGPU"), cl::Hidden, cl::init(false))
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))
static cl::opt< bool > EnableCopyHoist("hexagon-copy-hoist", cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("Enable Hexagon copy hoisting"))
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))
static cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
static cl::opt< bool > EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden, cl::desc("Generate absolute set instructions"))
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))
static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
static cl::opt< bool > EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true), cl::Hidden, cl::desc("Cleanup of TFRs/COPYs"))
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
cl::opt< unsigned > RDFFuncBlockLimit("rdf-bb-limit", cl::Hidden, cl::init(1000), cl::desc("Basic block limit for a function for RDF optimizations"))
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))
This file implements a TargetTransformInfo analysis pass specific to the Hexagon target machine.
static LVOptions Options
Definition: LVOptions.cpp:25
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
Module.h This file contains the declarations for the Module class.
const char LLVMTargetMachineRef TM
PassBuilder PB(Machine, PassOpts->PTO, std::nullopt, &PIC)
Basic Register Allocator
Target-Independent Code Generator Pass Configuration Options pass.
Attribute getFnAttr(Attribute::AttrKind Kind) const
Return the attribute object that exists for the function.
Definition: Attributes.h:864
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:391
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:203
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:311
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
void registerPassBuilderCallbacks(PassBuilder &PB, bool PopulateClassToPassNames) override
Allow the target to modify the pass pipeline.
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
MachineSchedRegistry provides a selection of available machine instruction schedulers.
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:106
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:420
void registerLoopOptimizerEndEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:430
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:94
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:575
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:576
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:223
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
std::string TargetFS
Definition: TargetMachine.h:98
std::string TargetCPU
Definition: TargetMachine.h:97
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Interfaces for registering analysis passes, producing common pass manager configurations,...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:443
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createHexagonVectorPrint()
FunctionPass * createHexagonCopyHoisting()
FunctionPass * createHexagonVectorCombineLegacyPass()
void initializeHexagonOptAddrModePass(PassRegistry &)
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
void initializeHexagonNewValueJumpPass(PassRegistry &)
char & HexagonTfrCleanupID
FunctionPass * createHexagonCFGOptimizer()
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
void initializeHexagonDAGToDAGISelLegacyPass(PassRegistry &)
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:145
Pass * createHexagonLoopIdiomPass()
FunctionPass * createHexagonNewValueJump()
void initializeHexagonRDFOptPass(PassRegistry &)
FunctionPass * createHexagonBranchRelaxation()
FunctionPass * createHexagonLoopAlign()
void initializeHexagonGenMemAbsolutePass(PassRegistry &Registry)
FunctionPass * createHexagonBitSimplify()
FunctionPass * createHexagonPeephole()
FunctionPass * createHexagonConstExtenders()
FunctionPass * createHexagonConstPropagationPass()
FunctionPass * createHexagonFixupHwLoops()
void initializeHexagonCopyHoistingPass(PassRegistry &Registry)
Target & getTheHexagonTarget()
void initializeHexagonExpandCondsetsPass(PassRegistry &)
void initializeHexagonPacketizerPass(PassRegistry &)
FunctionPass * createHexagonPacketizer(bool Minimal)
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
CodeModel::Model getEffectiveCodeModel(std::optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
FunctionPass * createHexagonGenMux()
FunctionPass * createHexagonGenExtract()
FunctionPass * createHexagonEarlyIfConversion()
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createHexagonCallFrameInformation()
void initializeHexagonTfrCleanupPass(PassRegistry &)
FunctionPass * createHexagonVExtract()
FunctionPass * createHexagonGenPredicate()
void initializeHexagonVectorCombineLegacyPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createHexagonGenInsert()
FunctionPass * createHexagonOptimizeSZextends()
FunctionPass * createHexagonLoopRescheduling()
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
FunctionPass * createHexagonSplitConst32AndConst64()
FunctionPass * createHexagonCopyToCombine()
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
FunctionPass * createHexagonCommonGEP()
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOptLevel OptLevel)
createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...
char & HexagonExpandCondsetsID
FunctionPass * createHexagonOptAddrMode()
void initializeHexagonCopyToCombinePass(PassRegistry &)
FunctionPass * createHexagonGenMemAbsolute()
void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)
char & VirtRegRewriterID
VirtRegRewriter pass.
Definition: VirtRegMap.cpp:227
FunctionPass * createHexagonTfrCleanup()
FunctionPass * createHexagonSplitDoubleRegs()
FunctionPass * createHexagonHardwareLoops()
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Pass * createHexagonVectorLoopCarriedReuseLegacyPass()
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
void initializeHexagonConstExtendersPass(PassRegistry &)
FunctionPass * createHexagonStoreWidening()
void initializeHexagonGenMuxPass(PassRegistry &Registry)
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
void initializeHexagonLoopAlignPass(PassRegistry &)
void initializeHexagonHardwareLoopsPass(PassRegistry &)
char & HexagonCopyHoistingID
FunctionPass * createHexagonRDFOpt()
FunctionPass * createInstSimplifyLegacyPass()
void initializeHexagonVExtractPass(PassRegistry &)
Implement std::hash so that hash_code can be used in STL containers.
Definition: BitVector.h:858
Hexagon Vector Loop Carried Reuse Pass.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
RegisterTargetMachine - Helper template for registering a target machine implementation,...