LLVM  15.0.0git
HexagonTargetMachine.cpp
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1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about Hexagon target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "HexagonTargetMachine.h"
14 #include "Hexagon.h"
15 #include "HexagonISelLowering.h"
22 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/Module.h"
27 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Transforms/Scalar.h"
32 
33 using namespace llvm;
34 
35 static cl::opt<bool>
36  EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true),
37  cl::desc("Enable Hexagon constant-extender optimization"));
38 
39 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true),
40  cl::desc("Enable RDF-based optimizations"));
41 
42 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
43  cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
44 
45 static cl::opt<bool>
46  DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden,
47  cl::desc("Disable Hexagon Addressing Mode Optimization"));
48 
49 static cl::opt<bool>
50  DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden,
51  cl::desc("Disable Hexagon CFG Optimization"));
52 
53 static cl::opt<bool>
54  DisableHCP("disable-hcp", cl::Hidden,
55  cl::desc("Disable Hexagon constant propagation"));
56 
57 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
58  cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
59 
60 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
61  cl::init(true), cl::Hidden,
62  cl::desc("Early expansion of MUX"));
63 
64 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
65  cl::desc("Enable early if-conversion"));
66 
67 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
68  cl::Hidden, cl::desc("Generate \"insert\" instructions"));
69 
70 static cl::opt<bool>
71  EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden,
72  cl::desc("Enable commoning of GEP instructions"));
73 
74 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
75  cl::Hidden, cl::desc("Generate \"extract\" instructions"));
76 
77 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
78  cl::desc("Enable converting conditional transfers into MUX instructions"));
79 
80 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
81  cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
82  "predicate instructions"));
83 
84 static cl::opt<bool>
85  EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden,
86  cl::desc("Enable loop data prefetch on Hexagon"));
87 
88 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
89  cl::desc("Disable splitting double registers"));
90 
91 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
92  cl::Hidden, cl::desc("Bit simplification"));
93 
94 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
95  cl::Hidden, cl::desc("Loop rescheduling"));
96 
97 static cl::opt<bool> HexagonNoOpt("hexagon-noopt", cl::init(false),
98  cl::Hidden, cl::desc("Disable backend optimizations"));
99 
100 static cl::opt<bool>
101  EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden,
102  cl::desc("Enable Hexagon Vector print instr pass"));
103 
104 static cl::opt<bool>
105  EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true),
106  cl::desc("Enable vextract optimization"));
107 
108 static cl::opt<bool>
109  EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true),
110  cl::desc("Enable HVX vector combining"));
111 
113  "hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true),
114  cl::desc("Simplify the CFG after atomic expansion pass"));
115 
116 static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
117  cl::init(true),
118  cl::desc("Enable instsimplify"));
119 
120 /// HexagonTargetMachineModule - Note that this is used on hosts that
121 /// cannot link in a library unless there are references into the
122 /// library. In particular, it seems that it is not possible to get
123 /// things to work on Win32 without this. Though it is unused, do not
124 /// remove it.
127 
130  C, std::make_unique<HexagonConvergingVLIWScheduler>());
131  DAG->addMutation(std::make_unique<HexagonSubtarget::UsrOverflowMutation>());
132  DAG->addMutation(std::make_unique<HexagonSubtarget::HVXMemLatencyMutation>());
133  DAG->addMutation(std::make_unique<HexagonSubtarget::CallMutation>());
135  return DAG;
136 }
137 
139 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
141 
142 namespace llvm {
143  extern char &HexagonExpandCondsetsID;
163 
180  CodeGenOpt::Level OptLevel);
185  FunctionPass *createHexagonPacketizer(bool Minimal);
194 } // end namespace llvm;
195 
197  return RM.value_or(Reloc::Static);
198 }
199 
201  // Register the target.
203 
221 }
222 
224  StringRef CPU, StringRef FS,
225  const TargetOptions &Options,
228  CodeGenOpt::Level OL, bool JIT)
229  // Specify the vector alignment explicitly. For v512x1, the calculated
230  // alignment would be 512*alignment(i1), which is 512 bytes, instead of
231  // the required minimum of 64 bytes.
233  T,
234  "e-m:e-p:32:32:32-a:0-n16:32-"
235  "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-"
236  "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048",
237  TT, CPU, FS, Options, getEffectiveRelocModel(RM),
239  (HexagonNoOpt ? CodeGenOpt::None : OL)),
240  TLOF(std::make_unique<HexagonTargetObjectFile>()) {
242  initAsmInfo();
243 }
244 
245 const HexagonSubtarget *
247  AttributeList FnAttrs = F.getAttributes();
248  Attribute CPUAttr =
249  FnAttrs.getFnAttr("target-cpu");
250  Attribute FSAttr =
251  FnAttrs.getFnAttr("target-features");
252 
253  std::string CPU =
254  CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
255  std::string FS =
256  FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
257  // Append the preexisting target features last, so that +mattr overrides
258  // the "unsafe-fp-math" function attribute.
259  // Creating a separate target feature is not strictly necessary, it only
260  // exists to make "unsafe-fp-math" force creating a new subtarget.
261 
262  if (F.getFnAttribute("unsafe-fp-math").getValueAsBool())
263  FS = FS.empty() ? "+unsafe-fp" : "+unsafe-fp," + FS;
264 
265  auto &I = SubtargetMap[CPU + FS];
266  if (!I) {
267  // This needs to be done before we create a new subtarget since any
268  // creation will depend on the TM and the code generation flags on the
269  // function that reside in TargetOptions.
271  I = std::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
272  }
273  return I.get();
274 }
275 
277  PMB.addExtension(
279  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
281  });
282  PMB.addExtension(
284  [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
286  });
287 }
288 
293  });
297  });
298 }
299 
302  return TargetTransformInfo(HexagonTTIImpl(this, F));
303 }
304 
306 
307 namespace {
308 /// Hexagon Code Generator Pass Configuration Options.
309 class HexagonPassConfig : public TargetPassConfig {
310 public:
311  HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
312  : TargetPassConfig(TM, PM) {}
313 
314  HexagonTargetMachine &getHexagonTargetMachine() const {
315  return getTM<HexagonTargetMachine>();
316  }
317 
319  createMachineScheduler(MachineSchedContext *C) const override {
320  return createVLIWMachineSched(C);
321  }
322 
323  void addIRPasses() override;
324  bool addInstSelector() override;
325  void addPreRegAlloc() override;
326  void addPostRegAlloc() override;
327  void addPreSched2() override;
328  void addPreEmitPass() override;
329 };
330 } // namespace
331 
333  return new HexagonPassConfig(*this, PM);
334 }
335 
336 void HexagonPassConfig::addIRPasses() {
338  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
339 
340  if (!NoOpt) {
341  if (EnableInstSimplify)
342  addPass(createInstSimplifyLegacyPass());
344  }
345 
346  addPass(createAtomicExpandPass());
347 
348  if (!NoOpt) {
351  .forwardSwitchCondToPhi(true)
352  .convertSwitchRangeToICmp(true)
353  .convertSwitchToLookupTable(true)
354  .needCanonicalLoops(false)
355  .hoistCommonInsts(true)
356  .sinkCommonInsts(true)));
357  if (EnableLoopPrefetch)
358  addPass(createLoopDataPrefetchPass());
361  if (EnableCommGEP)
362  addPass(createHexagonCommonGEP());
363  // Replace certain combinations of shifts and ands with extracts.
364  if (EnableGenExtract)
365  addPass(createHexagonGenExtract());
366  }
367 }
368 
369 bool HexagonPassConfig::addInstSelector() {
370  HexagonTargetMachine &TM = getHexagonTargetMachine();
371  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
372 
373  if (!NoOpt)
375 
376  addPass(createHexagonISelDag(TM, getOptLevel()));
377 
378  if (!NoOpt) {
379  if (EnableVExtractOpt)
380  addPass(createHexagonVExtract());
381  // Create logical operations on predicate registers.
382  if (EnableGenPred)
383  addPass(createHexagonGenPredicate());
384  // Rotate loops to expose bit-simplification opportunities.
385  if (EnableLoopResched)
387  // Split double registers.
388  if (!DisableHSDR)
389  addPass(createHexagonSplitDoubleRegs());
390  // Bit simplification.
391  if (EnableBitSimplify)
392  addPass(createHexagonBitSimplify());
393  addPass(createHexagonPeephole());
394  // Constant propagation.
395  if (!DisableHCP) {
398  }
399  if (EnableGenInsert)
400  addPass(createHexagonGenInsert());
401  if (EnableEarlyIf)
403  }
404 
405  return false;
406 }
407 
408 void HexagonPassConfig::addPreRegAlloc() {
409  if (getOptLevel() != CodeGenOpt::None) {
410  if (EnableCExtOpt)
411  addPass(createHexagonConstExtenders());
415  addPass(createHexagonStoreWidening());
417  addPass(createHexagonHardwareLoops());
418  }
419  if (TM->getOptLevel() >= CodeGenOpt::Default)
420  addPass(&MachinePipelinerID);
421 }
422 
423 void HexagonPassConfig::addPostRegAlloc() {
424  if (getOptLevel() != CodeGenOpt::None) {
425  if (EnableRDFOpt)
426  addPass(createHexagonRDFOpt());
428  addPass(createHexagonCFGOptimizer());
429  if (!DisableAModeOpt)
430  addPass(createHexagonOptAddrMode());
431  }
432 }
433 
434 void HexagonPassConfig::addPreSched2() {
435  addPass(createHexagonCopyToCombine());
436  if (getOptLevel() != CodeGenOpt::None)
437  addPass(&IfConverterID);
439 }
440 
441 void HexagonPassConfig::addPreEmitPass() {
442  bool NoOpt = (getOptLevel() == CodeGenOpt::None);
443 
444  if (!NoOpt)
445  addPass(createHexagonNewValueJump());
446 
448 
449  if (!NoOpt) {
451  addPass(createHexagonFixupHwLoops());
452  // Generate MUX from pairs of conditional transfers.
453  if (EnableGenMux)
454  addPass(createHexagonGenMux());
455  }
456 
457  // Packetization is mandatory: it handles gather/scatter at all opt levels.
458  addPass(createHexagonPacketizer(NoOpt));
459 
460  if (EnableVectorPrint)
461  addPass(createHexagonVectorPrint());
462 
463  // Add CFI instructions if necessary.
465 }
HexagonTargetInfo.h
EnableLoopResched
static cl::opt< bool > EnableLoopResched("hexagon-loop-resched", cl::init(true), cl::Hidden, cl::desc("Loop rescheduling"))
llvm::PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & >
Definition: LoopPassManager.h:69
EnableVectorCombine
static cl::opt< bool > EnableVectorCombine("hexagon-vector-combine", cl::Hidden, cl::init(true), cl::desc("Enable HVX vector combining"))
DisableStoreWidening
static cl::opt< bool > DisableStoreWidening("disable-store-widen", cl::Hidden, cl::init(false), cl::desc("Disable store widening"))
DisableHCP
static cl::opt< bool > DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation"))
llvm::createHexagonBranchRelaxation
FunctionPass * createHexagonBranchRelaxation()
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
PassBuilder.h
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:182
EnableVectorPrint
static cl::opt< bool > EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, cl::desc("Enable Hexagon Vector print instr pass"))
llvm::createHexagonLoopIdiomPass
Pass * createHexagonLoopIdiomPass()
Definition: HexagonLoopIdiomRecognition.cpp:2458
llvm::createHexagonNewValueJump
FunctionPass * createHexagonNewValueJump()
Definition: HexagonNewValueJump.cpp:720
llvm::createHexagonCallFrameInformation
FunctionPass * createHexagonCallFrameInformation()
llvm::createHexagonVectorLoopCarriedReuseLegacyPass
Pass * createHexagonVectorLoopCarriedReuseLegacyPass()
Definition: HexagonVectorLoopCarriedReuse.cpp:665
llvm::TargetOptions
Definition: TargetOptions.h:124
Scalar.h
T
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:65
EnableGenPred
static cl::opt< bool > EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " "predicate instructions"))
llvm::createCFGSimplificationPass
FunctionPass * createCFGSimplificationPass(SimplifyCFGOptions Options=SimplifyCFGOptions(), std::function< bool(const Function &)> Ftor=nullptr)
Definition: SimplifyCFGPass.cpp:432
llvm::MachinePipelinerID
char & MachinePipelinerID
This pass performs software pipelining on machine instructions.
Definition: MachinePipeliner.cpp:182
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::MachineSchedRegistry
MachineSchedRegistry provides a selection of available machine instruction schedulers.
Definition: MachineScheduler.h:141
llvm::createHexagonVectorCombineLegacyPass
FunctionPass * createHexagonVectorCombineLegacyPass()
Definition: HexagonVectorCombine.cpp:1529
llvm::initializeHexagonPacketizerPass
void initializeHexagonPacketizerPass(PassRegistry &)
llvm::HexagonTargetMachine
Definition: HexagonTargetMachine.h:25
llvm::createHexagonLoopRescheduling
FunctionPass * createHexagonLoopRescheduling()
Definition: HexagonBitSimplify.cpp:3397
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::initializeHexagonVectorCombineLegacyPass
void initializeHexagonVectorCombineLegacyPass(PassRegistry &)
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::HexagonTargetMachine::createPassConfig
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
Definition: HexagonTargetMachine.cpp:332
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
HexagonTargetTransformInfo.h
llvm::initializeHexagonOptAddrModePass
void initializeHexagonOptAddrModePass(PassRegistry &)
Module.h
llvm::AttributeList
Definition: Attributes.h:425
llvm::Optional< Reloc::Model >
llvm::VLIWMachineScheduler
Extend the standard ScheduleDAGMILive to provide more context and override the top-level schedule() d...
Definition: VLIWMachineScheduler.h:69
HexagonTargetMachineModule
int HexagonTargetMachineModule
HexagonTargetMachineModule - Note that this is used on hosts that cannot link in a library unless the...
Definition: HexagonTargetMachine.cpp:125
llvm::createHexagonCFGOptimizer
FunctionPass * createHexagonCFGOptimizer()
llvm::createHexagonGenExtract
FunctionPass * createHexagonGenExtract()
Definition: HexagonGenExtract.cpp:268
llvm::HexagonTargetObjectFile
Definition: HexagonTargetObjectFile.h:18
HexagonTargetMachine.h
llvm::createHexagonStoreWidening
FunctionPass * createHexagonStoreWidening()
Definition: HexagonStoreWidening.cpp:604
LegacyPassManager.h
PassManagerBuilder.h
llvm::initializeHexagonEarlyIfConversionPass
void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry)
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::PassManagerBuilder::EP_LoopOptimizerEnd
@ EP_LoopOptimizerEnd
EP_LoopOptimizerEnd - This extension point allows adding loop passes to the end of the loop optimizer...
Definition: PassManagerBuilder.h:78
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
EnableCommGEP
static cl::opt< bool > EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions"))
llvm::initializeHexagonVectorLoopCarriedReuseLegacyPassPass
void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &)
CommandLine.h
llvm::createHexagonSplitDoubleRegs
FunctionPass * createHexagonSplitDoubleRegs()
Definition: HexagonSplitDouble.cpp:1232
llvm::MSP430Attrs::CodeModel
CodeModel
Definition: MSP430Attributes.h:37
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::createHexagonEarlyIfConversion
FunctionPass * createHexagonEarlyIfConversion()
Definition: HexagonEarlyIfConv.cpp:1077
llvm::createHexagonRDFOpt
FunctionPass * createHexagonRDFOpt()
Definition: HexagonRDFOpt.cpp:339
llvm::createHexagonGenMux
FunctionPass * createHexagonGenMux()
Definition: HexagonGenMux.cpp:390
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
createVLIWMachineSched
static ScheduleDAGInstrs * createVLIWMachineSched(MachineSchedContext *C)
Definition: HexagonTargetMachine.cpp:128
llvm::PassBuilder
This class provides access to building LLVM's passes.
Definition: PassBuilder.h:94
llvm::createHexagonVExtract
FunctionPass * createHexagonVExtract()
Definition: HexagonVExtract.cpp:193
llvm::createCopyConstrainDAGMutation
std::unique_ptr< ScheduleDAGMutation > createCopyConstrainDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
Definition: MachineScheduler.cpp:1794
LLVMInitializeHexagonTarget
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeHexagonTarget()
Definition: HexagonTargetMachine.cpp:200
llvm::RegisterCoalescerID
char & RegisterCoalescerID
RegisterCoalescer - This pass merges live ranges to eliminate copies.
Definition: RegisterCoalescer.cpp:410
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::initializeHexagonExpandCondsetsPass
void initializeHexagonExpandCondsetsPass(PassRegistry &)
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
EnableGenMux
static cl::opt< bool > EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, cl::desc("Enable converting conditional transfers into MUX instructions"))
SchedCustomRegistry
static MachineSchedRegistry SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched)
DisableHardwareLoops
static cl::opt< bool > DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"))
llvm::createHexagonISelDag
FunctionPass * createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel)
createHexagonISelDag - This pass converts a legalized DAG into a Hexagon-specific DAG,...
Definition: HexagonISelDAGToDAG.cpp:60
llvm::HexagonTargetMachine::registerPassBuilderCallbacks
void registerPassBuilderCallbacks(PassBuilder &PB) override
Allow the target to modify the pass pipeline with New Pass Manager (similar to adjustPassManager for ...
Definition: HexagonTargetMachine.cpp:289
llvm::initializeHexagonBitSimplifyPass
void initializeHexagonBitSimplifyPass(PassRegistry &Registry)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::StringRef::str
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:249
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::None
const NoneType None
Definition: None.h:24
EnableInstSimplify
static cl::opt< bool > EnableInstSimplify("hexagon-instsimplify", cl::Hidden, cl::init(true), cl::desc("Enable instsimplify"))
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
Hexagon.h
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::HexagonLoopIdiomRecognitionPass
Definition: HexagonLoopIdiomRecognition.h:17
llvm::legacy::PassManagerBase::add
virtual void add(Pass *P)=0
Add a pass to the queue of passes to run.
llvm::PassManagerBuilder
PassManagerBuilder - This class is used to set up a standard optimization sequence for languages like...
Definition: PassManagerBuilder.h:57
llvm::createHexagonGenInsert
FunctionPass * createHexagonGenInsert()
Definition: HexagonGenInsert.cpp:1600
PB
PassBuilder PB(Machine, PassOpts->PTO, None, &PIC)
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
llvm::cl::opt< bool >
llvm::initializeHexagonNewValueJumpPass
void initializeHexagonNewValueJumpPass(PassRegistry &)
llvm::createHexagonConstExtenders
FunctionPass * createHexagonConstExtenders()
Definition: HexagonConstExtenders.cpp:2023
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::createHexagonBitSimplify
FunctionPass * createHexagonBitSimplify()
Definition: HexagonBitSimplify.cpp:3401
llvm::createHexagonOptimizeSZextends
FunctionPass * createHexagonOptimizeSZextends()
Definition: HexagonOptimizeSZextends.cpp:143
llvm::CodeGenOpt::Default
@ Default
Definition: CodeGen.h:55
HexagonNoOpt
static cl::opt< bool > HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, cl::desc("Disable backend optimizations"))
llvm::createHexagonVectorPrint
FunctionPass * createHexagonVectorPrint()
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
llvm::initializeHexagonLoopIdiomRecognizeLegacyPassPass
void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &)
DisableAModeOpt
static cl::opt< bool > DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, cl::desc("Disable Hexagon Addressing Mode Optimization"))
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::createHexagonConstPropagationPass
FunctionPass * createHexagonConstPropagationPass()
Definition: HexagonConstPropagation.cpp:3186
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
EnableBitSimplify
static cl::opt< bool > EnableBitSimplify("hexagon-bit", cl::init(true), cl::Hidden, cl::desc("Bit simplification"))
TargetPassConfig.h
llvm::createHexagonCopyToCombine
FunctionPass * createHexagonCopyToCombine()
Definition: HexagonCopyToCombine.cpp:877
EnableExpandCondsets
static cl::opt< bool > EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, cl::desc("Early expansion of MUX"))
llvm::X86AS::FS
@ FS
Definition: X86.h:192
HexagonVectorLoopCarriedReuse.h
HexagonMachineScheduler.h
llvm::HexagonExpandCondsetsID
char & HexagonExpandCondsetsID
Definition: HexagonExpandCondsets.cpp:249
llvm::PassBuilder::registerLoopOptimizerEndEPCallback
void registerLoopOptimizerEndEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:416
HexagonISelLowering.h
EnableVExtractOpt
static cl::opt< bool > EnableVExtractOpt("hexagon-opt-vextract", cl::Hidden, cl::init(true), cl::desc("Enable vextract optimization"))
llvm::createHexagonSplitConst32AndConst64
FunctionPass * createHexagonSplitConst32AndConst64()
Definition: HexagonSplitConst32AndConst64.cpp:109
llvm::PassBuilder::registerLateLoopOptimizationsEPCallback
void registerLateLoopOptimizationsEPCallback(const std::function< void(LoopPassManager &, OptimizationLevel)> &C)
Register a callback for a default optimizer pipeline extension point.
Definition: PassBuilder.h:406
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:471
llvm::getTheHexagonTarget
Target & getTheHexagonTarget()
Definition: HexagonTargetInfo.cpp:13
llvm::ScheduleDAG::TRI
const TargetRegisterInfo * TRI
Target processor register info.
Definition: ScheduleDAG.h:559
llvm::UnreachableMachineBlockElimID
char & UnreachableMachineBlockElimID
UnreachableMachineBlockElimination - This pass removes unreachable machine basic blocks.
llvm::createHexagonCommonGEP
FunctionPass * createHexagonCommonGEP()
Definition: HexagonCommonGEP.cpp:1291
llvm::createHexagonFixupHwLoops
FunctionPass * createHexagonFixupHwLoops()
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
llvm::initializeHexagonConstPropagationPass
void initializeHexagonConstPropagationPass(PassRegistry &Registry)
llvm::createHexagonOptAddrMode
FunctionPass * createHexagonOptAddrMode()
Definition: HexagonOptAddrMode.cpp:903
llvm::PassManager< Loop, LoopAnalysisManager, LoopStandardAnalysisResults &, LPMUpdater & >::addPass
LLVM_ATTRIBUTE_MINSIZE std::enable_if_t< is_detected< HasRunOnLoopT, PassT >::value > addPass(PassT &&Pass)
Definition: LoopPassManager.h:107
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::initializeHexagonConstExtendersPass
void initializeHexagonConstExtendersPass(PassRegistry &)
HexagonTargetObjectFile.h
llvm::PICLevel::Level
Level
Definition: CodeGen.h:33
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::getEffectiveCodeModel
CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM, CodeModel::Model Default)
Helper method for getting the code model, returning Default if CM does not have a value.
Definition: TargetMachine.h:506
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
EnableLoopPrefetch
static cl::opt< bool > EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon"))
llvm::HexagonTargetMachine::adjustPassManager
void adjustPassManager(PassManagerBuilder &PMB) override
Allow the target to modify the pass manager, e.g.
Definition: HexagonTargetMachine.cpp:276
llvm::initializeHexagonCopyToCombinePass
void initializeHexagonCopyToCombinePass(PassRegistry &)
DisableHSDR
static cl::opt< bool > DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, cl::desc("Disable splitting double registers"))
HexagonLoopIdiomRecognition.h
DisableHexagonCFGOpt
static cl::opt< bool > DisableHexagonCFGOpt("disable-hexagon-cfgopt", cl::Hidden, cl::desc("Disable Hexagon CFG Optimization"))
std
Definition: BitVector.h:851
llvm::HexagonTargetMachine::~HexagonTargetMachine
~HexagonTargetMachine() override
llvm::createHexagonPacketizer
FunctionPass * createHexagonPacketizer(bool Minimal)
Definition: HexagonVLIWPacketizer.cpp:1953
llvm::initializeHexagonSplitDoubleRegsPass
void initializeHexagonSplitDoubleRegsPass(PassRegistry &)
llvm::HexagonTargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: HexagonTargetMachine.cpp:301
EnableRDFOpt
static cl::opt< bool > EnableRDFOpt("rdf-opt", cl::Hidden, cl::init(true), cl::desc("Enable RDF-based optimizations"))
llvm::ScheduleDAG::TII
const TargetInstrInfo * TII
Target instruction information.
Definition: ScheduleDAG.h:558
EnableInitialCFGCleanup
static cl::opt< bool > EnableInitialCFGCleanup("hexagon-initial-cfg-cleanup", cl::Hidden, cl::init(true), cl::desc("Simplify the CFG after atomic expansion pass"))
VLIWMachineScheduler.h
llvm::OptimizationLevel
Definition: OptimizationLevel.h:22
llvm::HexagonTargetMachine::HexagonTargetMachine
HexagonTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Definition: HexagonTargetMachine.cpp:223
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:414
llvm::createInstSimplifyLegacyPass
FunctionPass * createInstSimplifyLegacyPass()
Definition: InstSimplifyPass.cpp:125
llvm::PassManagerBuilder::EP_LateLoopOptimizations
@ EP_LateLoopOptimizations
EP_LateLoopOptimizations - This extension point allows adding late loop canonicalization and simplifi...
Definition: PassManagerBuilder.h:110
llvm::initializeHexagonGenMuxPass
void initializeHexagonGenMuxPass(PassRegistry &Registry)
EnableGenExtract
static cl::opt< bool > EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, cl::desc("Generate \"extract\" instructions"))
llvm::HexagonTargetMachine::getSubtargetImpl
const HexagonSubtarget * getSubtargetImpl(const Function &F) const override
Virtual method implemented by subclasses that returns a reference to that target's TargetSubtargetInf...
Definition: HexagonTargetMachine.cpp:246
llvm::SimplifyCFGOptions
Definition: SimplifyCFGOptions.h:23
EnableEarlyIf
static cl::opt< bool > EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion"))
llvm::Pass
Pass interface - Implemented by all 'passes'.
Definition: Pass.h:91
llvm::HexagonVectorLoopCarriedReusePass
Hexagon Vector Loop Carried Reuse Pass.
Definition: HexagonVectorLoopCarriedReuse.h:128
EnableCExtOpt
static cl::opt< bool > EnableCExtOpt("hexagon-cext", cl::Hidden, cl::init(true), cl::desc("Enable Hexagon constant-extender optimization"))
llvm::HexagonSubtarget
Definition: HexagonSubtarget.h:43
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::createHexagonPeephole
FunctionPass * createHexagonPeephole()
Definition: HexagonPeephole.cpp:291
llvm::initializeHexagonRDFOptPass
void initializeHexagonRDFOptPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::FunctionPass
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:308
llvm::createDeadCodeEliminationPass
FunctionPass * createDeadCodeEliminationPass()
Definition: DCE.cpp:178
llvm::PassManagerBuilder::addExtension
void addExtension(ExtensionPointTy Ty, ExtensionFn Fn)
Definition: PassManagerBuilder.cpp:254
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::createHexagonHardwareLoops
FunctionPass * createHexagonHardwareLoops()
Definition: HexagonHardwareLoops.cpp:374
llvm::IfConverterID
char & IfConverterID
IfConverter - This pass performs machine code if conversion.
Definition: IfConversion.cpp:434
EnableGenInsert
static cl::opt< bool > EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, cl::desc("Generate \"insert\" instructions"))
llvm::AttributeList::getFnAttr
Attribute getFnAttr(Attribute::AttrKind Kind) const
Return the attribute object that exists for the function.
Definition: Attributes.h:810
TargetRegistry.h
llvm::HexagonTTIImpl
Definition: HexagonTargetTransformInfo.h:33
llvm::initializeHexagonHardwareLoopsPass
void initializeHexagonHardwareLoopsPass(PassRegistry &)
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::createHexagonGenPredicate
FunctionPass * createHexagonGenPredicate()
Definition: HexagonGenPredicate.cpp:536
llvm::createLoopDataPrefetchPass
FunctionPass * createLoopDataPrefetchPass()
Definition: LoopDataPrefetch.cpp:152
llvm::initializeHexagonVExtractPass
void initializeHexagonVExtractPass(PassRegistry &)