122#define DEBUG_TYPE "expand-condsets"
171 bool CoaLimitActive =
false;
172 bool TfrLimitActive =
false;
175 unsigned CoaCounter = 0;
176 unsigned TfrCounter = 0;
181 Sub(
Op.getSubReg()) {}
182 RegisterRef(
unsigned R = 0,
unsigned S = 0) :
Reg(
R), Sub(S) {}
185 return Reg == RR.Reg && Sub == RR.Sub;
189 return Reg < RR.Reg || (
Reg == RR.Reg && Sub < RR.Sub);
197 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
198 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
200 unsigned getMaskForSub(
unsigned Sub);
204 void addRefToMap(RegisterRef RR, ReferenceMap &Map,
unsigned Exec);
205 bool isRefInMap(RegisterRef, ReferenceMap &Map,
unsigned Exec);
210 void recalculateLiveInterval(
Register Reg);
212 void updateLiveness(
const std::set<Register> &RegSet,
bool Recalc,
213 bool UpdateKills,
bool UpdateDeads);
214 void distributeLiveIntervals(
const std::set<Register> &Regs);
220 bool ReadUndef,
bool ImpUse);
231 std::set<Register> &UpdRegs);
232 void renameInRange(RegisterRef RO, RegisterRef RN,
unsigned PredR,
238 bool isIntReg(RegisterRef RR,
unsigned &BW);
240 bool coalesceRegisters(RegisterRef R1, RegisterRef
R2);
242 std::set<Register> &UpdRegs);
247char HexagonExpandCondsets::ID = 0;
256 "Hexagon Expand Condsets",
false,
false)
263unsigned HexagonExpandCondsets::getMaskForSub(
unsigned Sub) {
265 case Hexagon::isub_lo:
266 case Hexagon::vsub_lo:
268 case Hexagon::isub_hi:
269 case Hexagon::vsub_hi:
271 case Hexagon::NoSubRegister:
278 unsigned Opc =
MI.getOpcode();
280 case Hexagon::C2_mux:
281 case Hexagon::C2_muxii:
282 case Hexagon::C2_muxir:
283 case Hexagon::C2_muxri:
284 case Hexagon::PS_pselect:
293 return Sub != 0 ?
TRI->getSubRegIndexLaneMask(Sub)
294 :
MRI->getMaxLaneMaskForVReg(Reg);
297void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
299 unsigned Mask = getMaskForSub(RR.Sub) |
Exec;
300 ReferenceMap::iterator
F =
Map.find(RR.Reg);
302 Map.insert(std::make_pair(RR.Reg, Mask));
307bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
309 ReferenceMap::iterator
F =
Map.find(RR.Reg);
312 unsigned Mask = getMaskForSub(RR.Sub) |
Exec;
313 if (Mask &
F->second)
318void HexagonExpandCondsets::updateKillFlags(
Register Reg) {
322 for (
unsigned i = 0, e =
MI->getNumOperands(); i !=
e; ++i) {
324 if (!
Op.isReg() || !
Op.isUse() ||
Op.getReg() !=
Reg ||
325 MI->isRegTiedToDefOperand(i))
328 if ((SLM & LM) == SLM) {
338 for (
auto I = LI.
begin(), E = LI.
end();
I != E; ++
I) {
339 if (!
I->end.isRegister())
343 auto NextI = std::next(
I);
344 if (NextI != E && NextI->start.isRegister()) {
345 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
346 if (HII->isPredicated(*DefI))
349 bool WholeReg =
true;
353 return F != S.end() &&
I->end ==
F->end;
359 KillAt(
I->end, S.LaneMask);
365 KillAt(
I->end,
MRI->getMaxLaneMaskForVReg(Reg));
377 if (!
Op.isReg() || !
Op.isDef())
378 return {
false,
false };
381 return {
false,
false };
384 return {
A.any(),
A == SLM };
397 if (
D != Dest && MDT->dominates(
D, Dest))
402 for (
unsigned i = 0; i < Work.size(); ++i) {
408 for (
auto *
P :
B->predecessors())
419 for (
auto &Seg : Range) {
420 if (!Seg.start.isRegister())
422 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
424 if (HII->isPredicated(*DefI))
432 for (
auto &SI : PredDefs) {
434 auto P =
Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
435 if (
P.first !=
nullptr ||
P.second)
442 for (
auto &SI : PredDefs) {
458 if (Dominate(Defs, BB))
463 LIS->extendToIndices(Range, ExtTo, Undefs);
472 std::set<RegisterRef> DefRegs;
473 for (
auto &Seg : Range) {
474 if (!Seg.start.isRegister())
476 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
478 auto P = IsRegDef(
Op);
479 if (
P.second && Seg.end.isDead()) {
481 }
else if (
P.first) {
490 for (
auto &Seg : Range) {
491 if (!Seg.start.isRegister() || !
Range.liveAt(Seg.start.getPrevSlot()))
493 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
494 if (!HII->isPredicated(*DefI))
499 std::map<RegisterRef,unsigned> ImpUses;
502 if (!
Op.isReg() || !DefRegs.count(
Op))
508 ImpUses.insert({
Op, i});
522 for (
auto [R, DefIdx] : ImpUses) {
529void HexagonExpandCondsets::updateDeadFlags(
Register Reg) {
533 updateDeadsInRange(Reg, S.LaneMask, S);
534 LIS->shrinkToUses(S, Reg);
537 LIS->constructMainRangeFromSubranges(LI);
539 updateDeadsInRange(Reg,
MRI->getMaxLaneMaskForVReg(Reg), LI);
543void HexagonExpandCondsets::recalculateLiveInterval(
Register Reg) {
544 LIS->removeInterval(Reg);
545 LIS->createAndComputeVirtRegInterval(Reg);
549 LIS->RemoveMachineInstrFromMaps(
MI);
550 MI.eraseFromParent();
553void HexagonExpandCondsets::updateLiveness(
const std::set<Register> &RegSet,
554 bool Recalc,
bool UpdateKills,
556 UpdateKills |= UpdateDeads;
558 if (!
R.isVirtual()) {
566 recalculateLiveInterval(R);
568 MRI->clearKillFlags(R);
575 LIS->getInterval(R).verify();
579void HexagonExpandCondsets::distributeLiveIntervals(
580 const std::set<Register> &Regs) {
586 unsigned NumComp = EQC.Classify(LI);
592 for (
unsigned I = 1;
I < NumComp; ++
I) {
594 NewLIs.
push_back(&LIS->createEmptyInterval(NewR));
596 EQC.Distribute(LI, NewLIs.
begin(), *
MRI);
602unsigned HexagonExpandCondsets::getCondTfrOpcode(
const MachineOperand &SO,
607 if (RS.Reg.isVirtual()) {
609 assert(
VC->begin() !=
VC->end() &&
"Empty register class");
610 PhysR = *
VC->begin();
614 MCRegister PhysS = (RS.Sub == 0) ? PhysR :
TRI->getSubReg(PhysR, RS.Sub);
616 switch (
TRI->getRegSizeInBits(*RC)) {
618 return IfTrue ? Hexagon::A2_tfrt : Hexagon::A2_tfrf;
620 return IfTrue ? Hexagon::A2_tfrpt : Hexagon::A2_tfrpf;
633 return IfTrue ? Hexagon::C2_cmoveit : Hexagon::C2_cmoveif;
647 bool PredSense,
bool ReadUndef,
bool ImpUse) {
658 unsigned Opc = getCondTfrOpcode(
SrcOp, PredSense);
660 unsigned PredState =
getRegState(PredOp) & ~RegState::Kill;
665 if (RegisterRef(
SrcOp) == RegisterRef(DstR, DstSR))
666 SrcState &= ~RegState::Kill;
668 .
addReg(DstR, DstState, DstSR)
673 .
addReg(DstR, DstState, DstSR)
685 std::set<Register> &UpdRegs) {
686 if (TfrLimitActive) {
687 if (TfrCounter >= TfrLimit)
701 for (
auto &
Op :
MI.operands()) {
703 UpdRegs.insert(
Op.getReg());
712 if (
ST.isReg() && SF.
isReg()) {
714 if (RT == RegisterRef(SF)) {
717 MI.setDesc(HII->get(TargetOpcode::COPY));
719 while (
MI.getNumOperands() > 1)
720 MI.removeOperand(
MI.getNumOperands()-1);
731 genCondTfrFor(ST, At, DR, DSR, MP,
true, ReadUndef,
false);
733 genCondTfrFor(SF, At, DR, DSR, MP,
false, ReadUndef,
true);
734 LIS->InsertMachineInstrInMaps(*TfrT);
735 LIS->InsertMachineInstrInMaps(*TfrF);
745 if (HII->isPredicated(*
MI) || !HII->isPredicable(*
MI))
747 if (
MI->hasUnmodeledSideEffects() ||
MI->mayStore())
751 for (
auto &
Op :
MI->operands()) {
752 if (!
Op.isReg() || !
Op.isDef())
758 for (
auto &Mo :
MI->memoperands()) {
759 if (Mo->isVolatile() || Mo->isAtomic())
768MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
775 bool PredValid =
true;
781 if (PredValid && HII->isPredicated(*
MI)) {
782 if (
MI->readsRegister(PredR) && (
Cond != HII->isPredicatedTrue(*
MI)))
788 for (
auto &
Op :
MI->operands()) {
789 if (!
Op.isReg() || !
Op.isDef())
792 if (RR.Reg == PredR) {
796 if (RR.Reg != RD.Reg)
801 if (RR.Sub == RD.Sub)
803 if (RR.Sub == 0 || RD.Sub == 0)
817bool HexagonExpandCondsets::canMoveOver(
MachineInstr &
MI, ReferenceMap &Defs,
818 ReferenceMap &
Uses) {
822 for (
auto &
Op :
MI.operands()) {
829 if (!RR.Reg.isVirtual())
832 if (isRefInMap(RR, Defs, Exec_Then))
835 if (
Op.isDef() && isRefInMap(RR,
Uses, Exec_Then))
846 if (!IsLoad && !IsStore)
848 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
859 if (
MI.hasUnmodeledSideEffects())
861 bool L =
MI.mayLoad(), S =
MI.mayStore();
864 if (Ordered &&
MI.hasOrderedMemoryRef())
867 bool Conflict = (
L && IsStore) || S;
876void HexagonExpandCondsets::predicateAt(
const MachineOperand &DefOp,
880 std::set<Register> &UpdRegs) {
894 unsigned Opc =
MI.getOpcode();
895 unsigned PredOpc = HII->getCondOpcode(Opc, !
Cond);
897 unsigned Ox = 0, NP =
MI.getNumOperands();
920 LIS->InsertMachineInstrInMaps(*NewI);
924 UpdRegs.insert(
Op.getReg());
931void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
938 if (!HII->isPredicated(
MI))
940 if (!
MI.readsRegister(PredR) || (
Cond != HII->isPredicatedTrue(
MI)))
943 for (
auto &
Op :
MI.operands()) {
944 if (!
Op.isReg() || RO != RegisterRef(
Op))
947 Op.setSubReg(
RN.Sub);
949 assert(!
Op.isDef() &&
"Not expecting a def");
958 std::set<Register> &UpdRegs) {
962 assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
982 if (!DefI || !isPredicable(DefI))
990 ReferenceMap
Uses, Defs;
996 bool PredValid =
true;
998 if (!
MI.modifiesRegister(PredR,
nullptr))
1009 unsigned Exec = Exec_Then | Exec_Else;
1010 if (PredValid && HII->isPredicated(
MI) &&
MI.readsRegister(PredR))
1011 Exec = (
Cond == HII->isPredicatedTrue(
MI)) ? Exec_Then : Exec_Else;
1013 for (
auto &
Op :
MI.operands()) {
1023 RegisterRef RR =
Op;
1024 if (!RR.Reg.isVirtual())
1027 ReferenceMap &
Map =
Op.isDef() ? Defs :
Uses;
1028 if (
Op.isDef() &&
Op.isUndef()) {
1029 assert(RR.Sub &&
"Expecting a subregister on <def,read-undef>");
1035 addRefToMap(RR, Map, Exec);
1052 if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT,
Uses, Exec_Else))
1054 RegisterRef RD = MD;
1061 bool CanUp = canMoveOver(TfrI, Defs,
Uses);
1062 bool CanDown = canMoveOver(*DefI, Defs,
Uses);
1066 if (!canMoveMemTo(*DefI, TfrI,
true))
1071 <<
", can move down: " << (CanDown ?
"yes\n" :
"no\n"));
1074 predicateAt(MD, *DefI, PastDefIt, MP,
Cond, UpdRegs);
1076 predicateAt(MD, *DefI, TfrIt, MP,
Cond, UpdRegs);
1081 renameInRange(RT, RD, PredR,
Cond, PastDefIt, TfrIt);
1082 UpdRegs.insert(RT.Reg);
1092 std::set<Register> &UpdRegs) {
1093 bool Changed =
false;
1095 unsigned Opc =
MI.getOpcode();
1096 if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
1097 bool Done = predicate(
MI, (Opc == Hexagon::A2_tfrt), UpdRegs);
1101 if (RegisterRef(
MI.getOperand(0)) == RegisterRef(
MI.getOperand(2))) {
1102 for (
auto &
Op :
MI.operands()) {
1104 UpdRegs.insert(
Op.getReg());
1115bool HexagonExpandCondsets::isIntReg(RegisterRef RR,
unsigned &BW) {
1116 if (!RR.Reg.isVirtual())
1119 if (RC == &Hexagon::IntRegsRegClass) {
1123 if (RC == &Hexagon::DoubleRegsRegClass) {
1124 BW = (RR.Sub != 0) ? 32 : 64;
1130bool HexagonExpandCondsets::isIntraBlocks(
LiveInterval &LI) {
1133 if (!LR.start.isRegister())
1136 if (!LR.end.isRegister() && !LR.end.isDead())
1142bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef
R2) {
1143 if (CoaLimitActive) {
1144 if (CoaCounter >= CoaLimit)
1151 if (
MRI->isLiveIn(R1.Reg))
1153 if (
MRI->isLiveIn(
R2.Reg))
1165 << (Overlap ?
"overlap" :
"disjoint") <<
")\n "
1166 <<
printReg(R1.Reg,
TRI, R1.Sub) <<
" " << L1 <<
"\n "
1168 if (R1.Sub ||
R2.Sub)
1176 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
1179 MRI->replaceRegWith(
R2.Reg, R1.Reg);
1185 VNInfo *NewVN, *OldVN =
I.valno;
1186 ValueInfoMap::iterator
F = VM.find(OldVN);
1187 if (
F == VM.end()) {
1188 NewVN = L1.
getNextValue(
I.valno->def, LIS->getVNInfoAllocator());
1189 VM.insert(std::make_pair(OldVN, NewVN));
1196 L2.removeSegment(*L2.begin());
1197 LIS->removeInterval(
R2.Reg);
1199 updateKillFlags(R1.Reg);
1209bool HexagonExpandCondsets::coalesceSegments(
1211 std::set<Register> &UpdRegs) {
1215 if (!
S1.isReg() && !S2.isReg())
1220 bool Changed =
false;
1222 RegisterRef RD = CI->getOperand(0);
1223 RegisterRef
RP = CI->getOperand(1);
1245 RegisterRef RS =
S1;
1246 MachineInstr *RDef = getReachingDefForPred(RS, CI,
RP.Reg,
true);
1247 if (!RDef || !HII->isPredicable(*RDef)) {
1248 Done = coalesceRegisters(RD, RegisterRef(
S1));
1250 UpdRegs.insert(RD.Reg);
1251 UpdRegs.insert(
S1.getReg());
1255 if (!
Done && S2.isReg()) {
1256 RegisterRef RS = S2;
1257 MachineInstr *RDef = getReachingDefForPred(RS, CI,
RP.Reg,
false);
1258 if (!RDef || !HII->isPredicable(*RDef)) {
1259 Done = coalesceRegisters(RD, RegisterRef(S2));
1261 UpdRegs.insert(RD.Reg);
1262 UpdRegs.insert(S2.getReg());
1271bool HexagonExpandCondsets::runOnMachineFunction(
MachineFunction &MF) {
1277 MDT = &getAnalysis<MachineDominatorTree>();
1278 LIS = &getAnalysis<LiveIntervals>();
1284 bool Changed =
false;
1285 std::set<Register> CoalUpd, PredUpd;
1288 for (
auto &
B : MF) {
1297 Changed |= coalesceSegments(
Condsets, CoalUpd);
1304 std::set<Register> KillUpd;
1307 if (
Op.isReg() &&
Op.isUse()) {
1308 if (!CoalUpd.count(
Op.getReg()))
1309 KillUpd.insert(
Op.getReg());
1315 LIS->print(
dbgs() <<
"After coalescing\n", MF.getFunction().getParent()));
1322 Changed |=
split(*
MI, PredUpd);
1332 LIS->print(
dbgs() <<
"After splitting\n", MF.getFunction().getParent()));
1339 Changed |= predicateInBlock(
B, PredUpd);
1341 MF.getFunction().getParent()));
1343 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1347 distributeLiveIntervals(PredUpd);
1351 LIS->print(
dbgs() <<
"After expand-condsets\n",
1352 MF.getFunction().getParent());
1362 return new HexagonExpandCondsets();
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
static Error split(StringRef Str, char Separator, std::pair< StringRef, StringRef > &Split)
Checked version of split, to ensure mandatory subparts.
This file defines the DenseMap class.
Rewrite Partial Register Uses
static Expected< BitVector > expand(StringRef S, StringRef Original)
static cl::opt< unsigned > OptCoaLimit("expand-condsets-coa-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"))
static cl::opt< unsigned > OptTfrLimit("expand-condsets-tfr-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"))
expand Hexagon Expand Condsets
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
static void updateLiveness(MachineFunction &MF)
Helper function to update the liveness information for the callee-saved registers.
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
This class represents an Operation in the Expression.
FunctionPass class - This class is used to implement most global optimizations.
Module * getParent()
Get the module that this global value is contained inside of...
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
void verify(const MachineRegisterInfo *MRI=nullptr) const
Walks the interval and assert if any invariants fail to hold.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
This class represents the liveness of a register, stack slot, etc.
iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
bool overlaps(const LiveRange &other) const
overlaps - Return true if the intersection of the two live ranges is not empty.
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
Wrapper class representing physical registers. Should be passed by value.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Function & getFunction()
Return the LLVM function that this machine code represents.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & cloneMemRefs(const MachineInstr &OtherMI) const
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool mayLoadOrStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read or modify memory.
const MachineBasicBlock * getParent() const
unsigned getNumOperands() const
Retuns the total number of operands.
bool mayLoad(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly read memory.
bool hasUnmodeledSideEffects() const
Return true if this instruction has side effects that are not modeled by mayLoad / mayStore,...
iterator_range< mop_iterator > operands()
void tieOperands(unsigned DefIdx, unsigned UseIdx)
Add a tie between the register operands at DefIdx and UseIdx.
bool hasOrderedMemoryRef() const
Return true if this instruction may have an ordered or volatile memory reference, or if the informati...
bool mayStore(QueryType Type=AnyInBundle) const
Return true if this instruction could possibly modify memory.
const MachineOperand & getOperand(unsigned i) const
void clearKillInfo()
Clears kill flags on all operands.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
Register getReg() const
getReg - Returns the register number.
@ MO_Immediate
Immediate operand.
@ MO_ConstantPoolIndex
Address of indexed Constant in Constant Pool.
@ MO_GlobalAddress
Address of a global value.
@ MO_BlockAddress
Address of a basic block.
@ MO_ExternalSymbol
Name of external global symbol.
@ MO_JumpTableIndex
Address of indexed Jump Table for switch.
@ MO_TargetIndex
Target-dependent index+offset operand.
@ MO_FPImmediate
Floating-point immediate operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
virtual StringRef getPassName() const
getPassName - Return a nice clean name for a pass.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
A vector that has set insertion semantics.
bool insert(const value_type &X)
Insert a new element into the SetVector.
SlotIndex - An opaque wrapper around machine indexes.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StringRef - Represent a constant reference to a string, i.e.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
VNInfo - Value Number Information.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
bool isIntReg(unsigned Reg)
@ Implicit
Not emitted register (e.g. carry, or temporary result).
@ Define
Register definition.
@ Undef
Value of the register doesn't matter.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool operator<(int64_t V1, const APSInt &V2)
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool operator!=(uint64_t V1, const APInt &V2)
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
FunctionPass * createHexagonExpandCondsets()
bool operator==(const AddressRangeValuePair &LHS, const AddressRangeValuePair &RHS)
void initializeHexagonExpandCondsetsPass(PassRegistry &)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
unsigned getRegState(const MachineOperand &RegOp)
Get all register state flags from machine operand RegOp.
char & HexagonExpandCondsetsID
DWARFExpression::Operation Op
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
This represents a simple continuous liveness interval for a value.