LLVM  10.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
49 #include <memory>
50 #include <string>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
55  cl::desc("Enable the machine combiner pass"),
56  cl::init(true), cl::Hidden);
57 
58 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
59  cl::desc("Enable the conditional branch "
60  "folding pass"),
61  cl::init(false), cl::Hidden);
62 
63 extern "C" void LLVMInitializeX86Target() {
64  // Register the target.
67 
85 }
86 
87 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
88  if (TT.isOSBinFormatMachO()) {
89  if (TT.getArch() == Triple::x86_64)
90  return std::make_unique<X86_64MachoTargetObjectFile>();
91  return std::make_unique<TargetLoweringObjectFileMachO>();
92  }
93 
94  if (TT.isOSFreeBSD())
95  return std::make_unique<X86FreeBSDTargetObjectFile>();
96  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
97  return std::make_unique<X86LinuxNaClTargetObjectFile>();
98  if (TT.isOSSolaris())
99  return std::make_unique<X86SolarisTargetObjectFile>();
100  if (TT.isOSFuchsia())
101  return std::make_unique<X86FuchsiaTargetObjectFile>();
102  if (TT.isOSBinFormatELF())
103  return std::make_unique<X86ELFTargetObjectFile>();
104  if (TT.isOSBinFormatCOFF())
105  return std::make_unique<TargetLoweringObjectFileCOFF>();
106  llvm_unreachable("unknown subtarget type");
107 }
108 
109 static std::string computeDataLayout(const Triple &TT) {
110  // X86 is little endian
111  std::string Ret = "e";
112 
114  // X86 and x32 have 32 bit pointers.
115  if ((TT.isArch64Bit() &&
116  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
117  !TT.isArch64Bit())
118  Ret += "-p:32:32";
119 
120  // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
121  Ret += "-p270:32:32-p271:32:32-p272:64:64";
122 
123  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
124  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
125  Ret += "-i64:64";
126  else if (TT.isOSIAMCU())
127  Ret += "-i64:32-f64:32";
128  else
129  Ret += "-f64:32:64";
130 
131  // Some ABIs align long double to 128 bits, others to 32.
132  if (TT.isOSNaCl() || TT.isOSIAMCU())
133  ; // No f80
134  else if (TT.isArch64Bit() || TT.isOSDarwin())
135  Ret += "-f80:128";
136  else
137  Ret += "-f80:32";
138 
139  if (TT.isOSIAMCU())
140  Ret += "-f128:32";
141 
142  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
143  if (TT.isArch64Bit())
144  Ret += "-n8:16:32:64";
145  else
146  Ret += "-n8:16:32";
147 
148  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
149  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
150  Ret += "-a:0:32-S32";
151  else
152  Ret += "-S128";
153 
154  return Ret;
155 }
156 
158  bool JIT,
160  bool is64Bit = TT.getArch() == Triple::x86_64;
161  if (!RM.hasValue()) {
162  // JIT codegen should use static relocations by default, since it's
163  // typically executed in process and not relocatable.
164  if (JIT)
165  return Reloc::Static;
166 
167  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
168  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
169  // use static relocation model by default.
170  if (TT.isOSDarwin()) {
171  if (is64Bit)
172  return Reloc::PIC_;
173  return Reloc::DynamicNoPIC;
174  }
175  if (TT.isOSWindows() && is64Bit)
176  return Reloc::PIC_;
177  return Reloc::Static;
178  }
179 
180  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
181  // is defined as a model for code which may be used in static or dynamic
182  // executables but not necessarily a shared library. On X86-32 we just
183  // compile in -static mode, in x86-64 we use PIC.
184  if (*RM == Reloc::DynamicNoPIC) {
185  if (is64Bit)
186  return Reloc::PIC_;
187  if (!TT.isOSDarwin())
188  return Reloc::Static;
189  }
190 
191  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
192  // the Mach-O file format doesn't support it.
193  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
194  return Reloc::PIC_;
195 
196  return *RM;
197 }
198 
200  bool JIT, bool Is64Bit) {
201  if (CM) {
202  if (*CM == CodeModel::Tiny)
203  report_fatal_error("Target does not support the tiny CodeModel", false);
204  return *CM;
205  }
206  if (JIT)
207  return Is64Bit ? CodeModel::Large : CodeModel::Small;
208  return CodeModel::Small;
209 }
210 
211 /// Create an X86 target.
212 ///
214  StringRef CPU, StringRef FS,
215  const TargetOptions &Options,
218  CodeGenOpt::Level OL, bool JIT)
220  T, computeDataLayout(TT), TT, CPU, FS, Options,
221  getEffectiveRelocModel(TT, JIT, RM),
222  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
223  OL),
224  TLOF(createTLOF(getTargetTriple())) {
225  // On PS4, the "return address" of a 'noreturn' call must still be within
226  // the calling function, and TrapUnreachable is an easy way to get that.
227  if (TT.isPS4() || TT.isOSBinFormatMachO()) {
228  this->Options.TrapUnreachable = true;
229  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
230  }
231 
232  // Outlining is available for x86-64.
233  if (TT.getArch() == Triple::x86_64)
234  setMachineOutliner(true);
235 
236  initAsmInfo();
237 }
238 
240 
241 const X86Subtarget *
243  Attribute CPUAttr = F.getFnAttribute("target-cpu");
244  Attribute FSAttr = F.getFnAttribute("target-features");
245 
246  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
247  ? CPUAttr.getValueAsString()
248  : (StringRef)TargetCPU;
250  ? FSAttr.getValueAsString()
251  : (StringRef)TargetFS;
252 
254  Key.reserve(CPU.size() + FS.size());
255  Key += CPU;
256  Key += FS;
257 
258  // FIXME: This is related to the code below to reset the target options,
259  // we need to know whether or not the soft float flag is set on the
260  // function before we can generate a subtarget. We also need to use
261  // it as a key for the subtarget since that can be the only difference
262  // between two functions.
263  bool SoftFloat =
264  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
265  // If the soft float attribute is set on the function turn on the soft float
266  // subtarget feature.
267  if (SoftFloat)
268  Key += FS.empty() ? "+soft-float" : ",+soft-float";
269 
270  // Keep track of the key width after all features are added so we can extract
271  // the feature string out later.
272  unsigned CPUFSWidth = Key.size();
273 
274  // Extract prefer-vector-width attribute.
275  unsigned PreferVectorWidthOverride = 0;
276  if (F.hasFnAttribute("prefer-vector-width")) {
277  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
278  unsigned Width;
279  if (!Val.getAsInteger(0, Width)) {
280  Key += ",prefer-vector-width=";
281  Key += Val;
282  PreferVectorWidthOverride = Width;
283  }
284  }
285 
286  // Extract min-legal-vector-width attribute.
287  unsigned RequiredVectorWidth = UINT32_MAX;
288  if (F.hasFnAttribute("min-legal-vector-width")) {
289  StringRef Val =
290  F.getFnAttribute("min-legal-vector-width").getValueAsString();
291  unsigned Width;
292  if (!Val.getAsInteger(0, Width)) {
293  Key += ",min-legal-vector-width=";
294  Key += Val;
295  RequiredVectorWidth = Width;
296  }
297  }
298 
299  // Extracted here so that we make sure there is backing for the StringRef. If
300  // we assigned earlier, its possible the SmallString reallocated leaving a
301  // dangling StringRef.
302  FS = Key.slice(CPU.size(), CPUFSWidth);
303 
304  auto &I = SubtargetMap[Key];
305  if (!I) {
306  // This needs to be done before we create a new subtarget since any
307  // creation will depend on the TM and the code generation flags on the
308  // function that reside in TargetOptions.
310  I = std::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
312  PreferVectorWidthOverride,
313  RequiredVectorWidth);
314  }
315  return I.get();
316 }
317 
318 //===----------------------------------------------------------------------===//
319 // Command line options for x86
320 //===----------------------------------------------------------------------===//
321 static cl::opt<bool>
322 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
323  cl::desc("Minimize AVX to SSE transition penalty"),
324  cl::init(true));
325 
326 //===----------------------------------------------------------------------===//
327 // X86 TTI query.
328 //===----------------------------------------------------------------------===//
329 
332  return TargetTransformInfo(X86TTIImpl(this, F));
333 }
334 
335 //===----------------------------------------------------------------------===//
336 // Pass Pipeline Configuration
337 //===----------------------------------------------------------------------===//
338 
339 namespace {
340 
341 /// X86 Code Generator Pass Configuration Options.
342 class X86PassConfig : public TargetPassConfig {
343 public:
344  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
345  : TargetPassConfig(TM, PM) {}
346 
347  X86TargetMachine &getX86TargetMachine() const {
348  return getTM<X86TargetMachine>();
349  }
350 
352  createMachineScheduler(MachineSchedContext *C) const override {
355  return DAG;
356  }
357 
359  createPostMachineScheduler(MachineSchedContext *C) const override {
362  return DAG;
363  }
364 
365  void addIRPasses() override;
366  bool addInstSelector() override;
367  bool addIRTranslator() override;
368  bool addLegalizeMachineIR() override;
369  bool addRegBankSelect() override;
370  bool addGlobalInstructionSelect() override;
371  bool addILPOpts() override;
372  bool addPreISel() override;
373  void addMachineSSAOptimization() override;
374  void addPreRegAlloc() override;
375  void addPostRegAlloc() override;
376  void addPreEmitPass() override;
377  void addPreEmitPass2() override;
378  void addPreSched2() override;
379 
380  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
381 };
382 
383 class X86ExecutionDomainFix : public ExecutionDomainFix {
384 public:
385  static char ID;
386  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
387  StringRef getPassName() const override {
388  return "X86 Execution Dependency Fix";
389  }
390 };
392 
393 } // end anonymous namespace
394 
395 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
396  "X86 Execution Domain Fix", false, false)
398 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
399  "X86 Execution Domain Fix", false, false)
400 
402  return new X86PassConfig(*this, PM);
403 }
404 
405 void X86PassConfig::addIRPasses() {
406  addPass(createAtomicExpandPass());
407 
409 
410  if (TM->getOptLevel() != CodeGenOpt::None)
411  addPass(createInterleavedAccessPass());
412 
413  // Add passes that handle indirect branch removal and insertion of a retpoline
414  // thunk. These will be a no-op unless a function subtarget has the retpoline
415  // feature enabled.
416  addPass(createIndirectBrExpandPass());
417 }
418 
419 bool X86PassConfig::addInstSelector() {
420  // Install an instruction selector.
421  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
422 
423  // For ELF, cleanup any local-dynamic TLS accesses.
424  if (TM->getTargetTriple().isOSBinFormatELF() &&
427 
428  addPass(createX86GlobalBaseRegPass());
429  return false;
430 }
431 
432 bool X86PassConfig::addIRTranslator() {
433  addPass(new IRTranslator());
434  return false;
435 }
436 
437 bool X86PassConfig::addLegalizeMachineIR() {
438  addPass(new Legalizer());
439  return false;
440 }
441 
442 bool X86PassConfig::addRegBankSelect() {
443  addPass(new RegBankSelect());
444  return false;
445 }
446 
447 bool X86PassConfig::addGlobalInstructionSelect() {
448  addPass(new InstructionSelect());
449  return false;
450 }
451 
452 bool X86PassConfig::addILPOpts() {
454  addPass(createX86CondBrFolding());
455  addPass(&EarlyIfConverterID);
457  addPass(&MachineCombinerID);
458  addPass(createX86CmovConverterPass());
459  return true;
460 }
461 
462 bool X86PassConfig::addPreISel() {
463  // Only add this pass for 32-bit x86 Windows.
464  const Triple &TT = TM->getTargetTriple();
465  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
466  addPass(createX86WinEHStatePass());
467  return true;
468 }
469 
470 void X86PassConfig::addPreRegAlloc() {
471  if (getOptLevel() != CodeGenOpt::None) {
472  addPass(&LiveRangeShrinkID);
473  addPass(createX86FixupSetCC());
474  addPass(createX86OptimizeLEAs());
477  }
478 
481  addPass(createX86WinAllocaExpander());
482 }
483 void X86PassConfig::addMachineSSAOptimization() {
486 }
487 
488 void X86PassConfig::addPostRegAlloc() {
490 }
491 
492 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
493 
494 void X86PassConfig::addPreEmitPass() {
495  if (getOptLevel() != CodeGenOpt::None) {
496  addPass(new X86ExecutionDomainFix());
497  addPass(createBreakFalseDeps());
498  }
499 
501 
502  if (UseVZeroUpper)
503  addPass(createX86IssueVZeroUpperPass());
504 
505  if (getOptLevel() != CodeGenOpt::None) {
506  addPass(createX86FixupBWInsts());
507  addPass(createX86PadShortFunctions());
508  addPass(createX86FixupLEAs());
509  addPass(createX86EvexToVexInsts());
510  }
512  addPass(createX86InsertPrefetchPass());
513 }
514 
515 void X86PassConfig::addPreEmitPass2() {
516  const Triple &TT = TM->getTargetTriple();
517  const MCAsmInfo *MAI = TM->getMCAsmInfo();
518 
519  addPass(createX86RetpolineThunksPass());
520 
521  // Insert extra int3 instructions after trailing call instructions to avoid
522  // issues in the unwinder.
523  if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
525 
526  // Verify basic block incoming and outgoing cfa offset and register values and
527  // correct CFA calculation rule where needed by inserting appropriate CFI
528  // instructions.
529  if (!TT.isOSDarwin() &&
530  (!TT.isOSWindows() ||
532  addPass(createCFIInstrInserter());
533 }
534 
535 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
536  return getStandardCSEConfigForOpt(TM->getOptLevel());
537 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:505
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:369
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:151
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:140
bool isOSSolaris() const
Definition: Triple.h:511
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
static cl::opt< bool > EnableCondBrFoldingPass("x86-condbr-folding", cl::desc("Enable the conditional branch " "folding pass"), cl::init(false), cl::Hidden)
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:259
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeX86CondBrFoldingPassPass(PassRegistry &)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:144
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:655
speculative execution
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
char & LiveRangeShrinkID
LiveRangeShrink pass.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:235
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
void initializeX86ExpandPseudoPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
size_t size() const
Definition: SmallVector.h:52
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:492
bool isOSIAMCU() const
Definition: Triple.h:515
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
FunctionPass * createX86SpeculativeLoadHardeningPass()
bool isOSFreeBSD() const
Definition: Triple.h:501
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:85
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
void initializeX86OptimizeLEAPassPass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:220
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction...
Target & getTheX86_32Target()
FunctionPass * createX86CondBrFolding()
Return a pass that folds conditional branch jumps.
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:593
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber, Discriminator> (with respect to eachother)
This pass exposes codegen information to IR-level passes.
DWARF-like instruction based exceptions.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.