LLVM  10.0.0svn
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
49 #include <memory>
50 #include <string>
51 
52 using namespace llvm;
53 
54 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
55  cl::desc("Enable the machine combiner pass"),
56  cl::init(true), cl::Hidden);
57 
58 static cl::opt<bool> EnableCondBrFoldingPass("x86-condbr-folding",
59  cl::desc("Enable the conditional branch "
60  "folding pass"),
61  cl::init(false), cl::Hidden);
62 
63 extern "C" void LLVMInitializeX86Target() {
64  // Register the target.
67 
85 }
86 
87 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
88  if (TT.isOSBinFormatMachO()) {
89  if (TT.getArch() == Triple::x86_64)
90  return std::make_unique<X86_64MachoTargetObjectFile>();
91  return std::make_unique<TargetLoweringObjectFileMachO>();
92  }
93 
94  if (TT.isOSFreeBSD())
95  return std::make_unique<X86FreeBSDTargetObjectFile>();
96  if (TT.isOSLinux() || TT.isOSNaCl() || TT.isOSIAMCU())
97  return std::make_unique<X86LinuxNaClTargetObjectFile>();
98  if (TT.isOSSolaris())
99  return std::make_unique<X86SolarisTargetObjectFile>();
100  if (TT.isOSFuchsia())
101  return std::make_unique<X86FuchsiaTargetObjectFile>();
102  if (TT.isOSBinFormatELF())
103  return std::make_unique<X86ELFTargetObjectFile>();
104  if (TT.isOSBinFormatCOFF())
105  return std::make_unique<TargetLoweringObjectFileCOFF>();
106  llvm_unreachable("unknown subtarget type");
107 }
108 
109 static std::string computeDataLayout(const Triple &TT) {
110  // X86 is little endian
111  std::string Ret = "e";
112 
114  // X86 and x32 have 32 bit pointers.
115  if ((TT.isArch64Bit() &&
116  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
117  !TT.isArch64Bit())
118  Ret += "-p:32:32";
119 
120  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
121  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
122  Ret += "-i64:64";
123  else if (TT.isOSIAMCU())
124  Ret += "-i64:32-f64:32";
125  else
126  Ret += "-f64:32:64";
127 
128  // Some ABIs align long double to 128 bits, others to 32.
129  if (TT.isOSNaCl() || TT.isOSIAMCU())
130  ; // No f80
131  else if (TT.isArch64Bit() || TT.isOSDarwin())
132  Ret += "-f80:128";
133  else
134  Ret += "-f80:32";
135 
136  if (TT.isOSIAMCU())
137  Ret += "-f128:32";
138 
139  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
140  if (TT.isArch64Bit())
141  Ret += "-n8:16:32:64";
142  else
143  Ret += "-n8:16:32";
144 
145  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
146  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
147  Ret += "-a:0:32-S32";
148  else
149  Ret += "-S128";
150 
151  return Ret;
152 }
153 
155  bool JIT,
157  bool is64Bit = TT.getArch() == Triple::x86_64;
158  if (!RM.hasValue()) {
159  // JIT codegen should use static relocations by default, since it's
160  // typically executed in process and not relocatable.
161  if (JIT)
162  return Reloc::Static;
163 
164  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
165  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
166  // use static relocation model by default.
167  if (TT.isOSDarwin()) {
168  if (is64Bit)
169  return Reloc::PIC_;
170  return Reloc::DynamicNoPIC;
171  }
172  if (TT.isOSWindows() && is64Bit)
173  return Reloc::PIC_;
174  return Reloc::Static;
175  }
176 
177  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
178  // is defined as a model for code which may be used in static or dynamic
179  // executables but not necessarily a shared library. On X86-32 we just
180  // compile in -static mode, in x86-64 we use PIC.
181  if (*RM == Reloc::DynamicNoPIC) {
182  if (is64Bit)
183  return Reloc::PIC_;
184  if (!TT.isOSDarwin())
185  return Reloc::Static;
186  }
187 
188  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
189  // the Mach-O file format doesn't support it.
190  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
191  return Reloc::PIC_;
192 
193  return *RM;
194 }
195 
197  bool JIT, bool Is64Bit) {
198  if (CM) {
199  if (*CM == CodeModel::Tiny)
200  report_fatal_error("Target does not support the tiny CodeModel", false);
201  return *CM;
202  }
203  if (JIT)
204  return Is64Bit ? CodeModel::Large : CodeModel::Small;
205  return CodeModel::Small;
206 }
207 
208 /// Create an X86 target.
209 ///
211  StringRef CPU, StringRef FS,
212  const TargetOptions &Options,
215  CodeGenOpt::Level OL, bool JIT)
217  T, computeDataLayout(TT), TT, CPU, FS, Options,
218  getEffectiveRelocModel(TT, JIT, RM),
219  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
220  OL),
221  TLOF(createTLOF(getTargetTriple())) {
222  // Windows stack unwinder gets confused when execution flow "falls through"
223  // after a call to 'noreturn' function.
224  // To prevent that, we emit a trap for 'unreachable' IR instructions.
225  // (which on X86, happens to be the 'ud2' instruction)
226  // On PS4, the "return address" of a 'noreturn' call must still be within
227  // the calling function, and TrapUnreachable is an easy way to get that.
228  // The check here for 64-bit windows is a bit icky, but as we're unlikely
229  // to ever want to mix 32 and 64-bit windows code in a single module
230  // this should be fine.
231  if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4() ||
232  TT.isOSBinFormatMachO()) {
233  this->Options.TrapUnreachable = true;
234  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
235  }
236 
237  // Outlining is available for x86-64.
238  if (TT.getArch() == Triple::x86_64)
239  setMachineOutliner(true);
240 
241  initAsmInfo();
242 }
243 
245 
246 const X86Subtarget *
248  Attribute CPUAttr = F.getFnAttribute("target-cpu");
249  Attribute FSAttr = F.getFnAttribute("target-features");
250 
251  StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
252  ? CPUAttr.getValueAsString()
253  : (StringRef)TargetCPU;
255  ? FSAttr.getValueAsString()
256  : (StringRef)TargetFS;
257 
259  Key.reserve(CPU.size() + FS.size());
260  Key += CPU;
261  Key += FS;
262 
263  // FIXME: This is related to the code below to reset the target options,
264  // we need to know whether or not the soft float flag is set on the
265  // function before we can generate a subtarget. We also need to use
266  // it as a key for the subtarget since that can be the only difference
267  // between two functions.
268  bool SoftFloat =
269  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
270  // If the soft float attribute is set on the function turn on the soft float
271  // subtarget feature.
272  if (SoftFloat)
273  Key += FS.empty() ? "+soft-float" : ",+soft-float";
274 
275  // Keep track of the key width after all features are added so we can extract
276  // the feature string out later.
277  unsigned CPUFSWidth = Key.size();
278 
279  // Extract prefer-vector-width attribute.
280  unsigned PreferVectorWidthOverride = 0;
281  if (F.hasFnAttribute("prefer-vector-width")) {
282  StringRef Val = F.getFnAttribute("prefer-vector-width").getValueAsString();
283  unsigned Width;
284  if (!Val.getAsInteger(0, Width)) {
285  Key += ",prefer-vector-width=";
286  Key += Val;
287  PreferVectorWidthOverride = Width;
288  }
289  }
290 
291  // Extract min-legal-vector-width attribute.
292  unsigned RequiredVectorWidth = UINT32_MAX;
293  if (F.hasFnAttribute("min-legal-vector-width")) {
294  StringRef Val =
295  F.getFnAttribute("min-legal-vector-width").getValueAsString();
296  unsigned Width;
297  if (!Val.getAsInteger(0, Width)) {
298  Key += ",min-legal-vector-width=";
299  Key += Val;
300  RequiredVectorWidth = Width;
301  }
302  }
303 
304  // Extracted here so that we make sure there is backing for the StringRef. If
305  // we assigned earlier, its possible the SmallString reallocated leaving a
306  // dangling StringRef.
307  FS = Key.slice(CPU.size(), CPUFSWidth);
308 
309  auto &I = SubtargetMap[Key];
310  if (!I) {
311  // This needs to be done before we create a new subtarget since any
312  // creation will depend on the TM and the code generation flags on the
313  // function that reside in TargetOptions.
315  I = std::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
317  PreferVectorWidthOverride,
318  RequiredVectorWidth);
319  }
320  return I.get();
321 }
322 
323 //===----------------------------------------------------------------------===//
324 // Command line options for x86
325 //===----------------------------------------------------------------------===//
326 static cl::opt<bool>
327 UseVZeroUpper("x86-use-vzeroupper", cl::Hidden,
328  cl::desc("Minimize AVX to SSE transition penalty"),
329  cl::init(true));
330 
331 //===----------------------------------------------------------------------===//
332 // X86 TTI query.
333 //===----------------------------------------------------------------------===//
334 
337  return TargetTransformInfo(X86TTIImpl(this, F));
338 }
339 
340 //===----------------------------------------------------------------------===//
341 // Pass Pipeline Configuration
342 //===----------------------------------------------------------------------===//
343 
344 namespace {
345 
346 /// X86 Code Generator Pass Configuration Options.
347 class X86PassConfig : public TargetPassConfig {
348 public:
349  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
350  : TargetPassConfig(TM, PM) {}
351 
352  X86TargetMachine &getX86TargetMachine() const {
353  return getTM<X86TargetMachine>();
354  }
355 
357  createMachineScheduler(MachineSchedContext *C) const override {
360  return DAG;
361  }
362 
364  createPostMachineScheduler(MachineSchedContext *C) const override {
367  return DAG;
368  }
369 
370  void addIRPasses() override;
371  bool addInstSelector() override;
372  bool addIRTranslator() override;
373  bool addLegalizeMachineIR() override;
374  bool addRegBankSelect() override;
375  bool addGlobalInstructionSelect() override;
376  bool addILPOpts() override;
377  bool addPreISel() override;
378  void addMachineSSAOptimization() override;
379  void addPreRegAlloc() override;
380  void addPostRegAlloc() override;
381  void addPreEmitPass() override;
382  void addPreEmitPass2() override;
383  void addPreSched2() override;
384 
385  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
386 };
387 
388 class X86ExecutionDomainFix : public ExecutionDomainFix {
389 public:
390  static char ID;
391  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
392  StringRef getPassName() const override {
393  return "X86 Execution Dependency Fix";
394  }
395 };
397 
398 } // end anonymous namespace
399 
400 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
401  "X86 Execution Domain Fix", false, false)
403 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
404  "X86 Execution Domain Fix", false, false)
405 
407  return new X86PassConfig(*this, PM);
408 }
409 
410 void X86PassConfig::addIRPasses() {
411  addPass(createAtomicExpandPass());
412 
414 
415  if (TM->getOptLevel() != CodeGenOpt::None)
416  addPass(createInterleavedAccessPass());
417 
418  // Add passes that handle indirect branch removal and insertion of a retpoline
419  // thunk. These will be a no-op unless a function subtarget has the retpoline
420  // feature enabled.
421  addPass(createIndirectBrExpandPass());
422 }
423 
424 bool X86PassConfig::addInstSelector() {
425  // Install an instruction selector.
426  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
427 
428  // For ELF, cleanup any local-dynamic TLS accesses.
429  if (TM->getTargetTriple().isOSBinFormatELF() &&
432 
433  addPass(createX86GlobalBaseRegPass());
434  return false;
435 }
436 
437 bool X86PassConfig::addIRTranslator() {
438  addPass(new IRTranslator());
439  return false;
440 }
441 
442 bool X86PassConfig::addLegalizeMachineIR() {
443  addPass(new Legalizer());
444  return false;
445 }
446 
447 bool X86PassConfig::addRegBankSelect() {
448  addPass(new RegBankSelect());
449  return false;
450 }
451 
452 bool X86PassConfig::addGlobalInstructionSelect() {
453  addPass(new InstructionSelect());
454  return false;
455 }
456 
457 bool X86PassConfig::addILPOpts() {
459  addPass(createX86CondBrFolding());
460  addPass(&EarlyIfConverterID);
462  addPass(&MachineCombinerID);
463  addPass(createX86CmovConverterPass());
464  return true;
465 }
466 
467 bool X86PassConfig::addPreISel() {
468  // Only add this pass for 32-bit x86 Windows.
469  const Triple &TT = TM->getTargetTriple();
470  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
471  addPass(createX86WinEHStatePass());
472  return true;
473 }
474 
475 void X86PassConfig::addPreRegAlloc() {
476  if (getOptLevel() != CodeGenOpt::None) {
477  addPass(&LiveRangeShrinkID);
478  addPass(createX86FixupSetCC());
479  addPass(createX86OptimizeLEAs());
482  }
483 
486  addPass(createX86WinAllocaExpander());
487 }
488 void X86PassConfig::addMachineSSAOptimization() {
491 }
492 
493 void X86PassConfig::addPostRegAlloc() {
495 }
496 
497 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
498 
499 void X86PassConfig::addPreEmitPass() {
500  if (getOptLevel() != CodeGenOpt::None) {
501  addPass(new X86ExecutionDomainFix());
502  addPass(createBreakFalseDeps());
503  }
504 
506 
507  if (UseVZeroUpper)
508  addPass(createX86IssueVZeroUpperPass());
509 
510  if (getOptLevel() != CodeGenOpt::None) {
511  addPass(createX86FixupBWInsts());
512  addPass(createX86PadShortFunctions());
513  addPass(createX86FixupLEAs());
514  addPass(createX86EvexToVexInsts());
515  }
517  addPass(createX86InsertPrefetchPass());
518 }
519 
520 void X86PassConfig::addPreEmitPass2() {
521  addPass(createX86RetpolineThunksPass());
522  // Verify basic block incoming and outgoing cfa offset and register values and
523  // correct CFA calculation rule where needed by inserting appropriate CFI
524  // instructions.
525  const Triple &TT = TM->getTargetTriple();
526  const MCAsmInfo *MAI = TM->getMCAsmInfo();
527  if (!TT.isOSDarwin() &&
528  (!TT.isOSWindows() ||
530  addPass(createCFIInstrInserter());
531 }
532 
533 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
534  return getStandardCSEConfigForOpt(TM->getOptLevel());
535 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
void LLVMInitializeX86Target()
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine...
static std::string computeDataLayout(const Triple &TT)
bool isOSNaCl() const
Tests whether the OS is NaCl (Native Client)
Definition: Triple.h:581
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:323
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
bool isOSFuchsia() const
Definition: Triple.h:505
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void reserve(size_type N)
Definition: SmallVector.h:369
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:156
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another, when profitable.
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:50
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
bool isOSSolaris() const
Definition: Triple.h:511
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
static cl::opt< bool > EnableCondBrFoldingPass("x86-condbr-folding", cl::desc("Enable the conditional branch " "folding pass"), cl::init(false), cl::Hidden)
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
Definition: SmallString.h:259
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
void initializeX86CondBrFoldingPassPass(PassRegistry &)
ArchType getArch() const
getArch - Get the parsed architecture type of this triple.
Definition: Triple.h:296
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec...
LLVM_NODISCARD size_t size() const
size - Get the string size.
Definition: StringRef.h:130
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
bool isPS4() const
Tests whether the target is the PS4 platform.
Definition: Triple.h:655
speculative execution
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
char & LiveRangeShrinkID
LiveRangeShrink pass.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:238
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
static bool is64Bit(const char *name)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
void initializeX86ExpandPseudoPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
size_t size() const
Definition: SmallVector.h:52
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
FunctionPass * createIndirectBrExpandPass()
std::enable_if< std::numeric_limits< T >::is_signed, bool >::type getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:478
bool isOSIAMCU() const
Definition: Triple.h:515
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
EnvironmentType getEnvironment() const
getEnvironment - Get the parsed environment type of this triple.
Definition: Triple.h:314
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
FunctionPass * createX86SpeculativeLoadHardeningPass()
bool isOSFreeBSD() const
Definition: Triple.h:501
This pass is responsible for selecting generic machine instructions to target-specific instructions...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:85
static cl::opt< bool > UseVZeroUpper("x86-use-vzeroupper", cl::Hidden, cl::desc("Minimize AVX to SSE transition penalty"), cl::init(true))
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
void initializeX86OptimizeLEAPassPass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
bool hasValue() const
Definition: Optional.h:259
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
bool isArch64Bit() const
Test whether the architecture is 64-bit.
Definition: Triple.cpp:1292
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling...
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
Target & getTheX86_32Target()
FunctionPass * createX86CondBrFolding()
Return a pass that folds conditional branch jumps.
std::string TargetFS
Definition: TargetMachine.h:86
FunctionPass * createX86RetpolineThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:576
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber, Discriminator> (with respect to eachother)
This pass exposes codegen information to IR-level passes.
DWARF-like instruction based exceptions.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates...
FunctionPass * createAtomicExpandPass()
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.