60 cl::desc(
"Enable the machine combiner pass"),
65 cl::desc(
"Enable the tile register allocation pass"),
112 if (TT.isOSBinFormatMachO()) {
114 return std::make_unique<X86_64MachoTargetObjectFile>();
115 return std::make_unique<TargetLoweringObjectFileMachO>();
118 if (TT.isOSBinFormatCOFF())
119 return std::make_unique<TargetLoweringObjectFileCOFF>();
122 return std::make_unique<X86_64ELFTargetObjectFile>();
123 return std::make_unique<X86ELFTargetObjectFile>();
128 std::string Ret =
"e";
132 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
136 Ret +=
"-p270:32:32-p271:32:32-p272:64:64";
141 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
142 Ret +=
"-i64:64-i128:128";
143 else if (TT.isOSIAMCU())
144 Ret +=
"-i64:32-f64:32";
146 Ret +=
"-i128:128-f64:32:64";
149 if (TT.isOSNaCl() || TT.isOSIAMCU())
151 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
160 if (TT.isArch64Bit())
161 Ret +=
"-n8:16:32:64";
166 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
167 Ret +=
"-a:0:32-S32";
175 std::optional<Reloc::Model> RM) {
186 if (TT.isOSDarwin()) {
191 if (TT.isOSWindows() &&
is64Bit)
203 if (!TT.isOSDarwin())
234 std::optional<Reloc::Model> RM,
235 std::optional<CodeModel::Model> CM,
242 TLOF(
createTLOF(getTargetTriple())), IsJIT(JIT) {
245 if (TT.isPS() || TT.isOSBinFormatMachO()) {
262 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
263 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
264 Attribute FSAttr =
F.getFnAttribute(
"target-features");
272 : CPU ==
"x86-64" ?
"generic"
284 unsigned PreferVectorWidthOverride = 0;
285 Attribute PreferVecWidthAttr =
F.getFnAttribute(
"prefer-vector-width");
286 if (PreferVecWidthAttr.
isValid()) {
292 PreferVectorWidthOverride = Width;
297 unsigned RequiredVectorWidth = UINT32_MAX;
298 Attribute MinLegalVecWidthAttr =
F.getFnAttribute(
"min-legal-vector-width");
299 if (MinLegalVecWidthAttr.
isValid()) {
305 RequiredVectorWidth = Width;
316 unsigned FSStart = Key.size();
323 bool SoftFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
327 Key += FS.empty() ?
"+soft-float" :
"+soft-float,";
333 FS = Key.substr(FSStart);
335 auto &
I = SubtargetMap[Key];
341 I = std::make_unique<X86Subtarget>(
343 MaybeAlign(
F.getParent()->getOverrideStackAlignment()),
344 PreferVectorWidthOverride, RequiredVectorWidth);
368 unsigned DestAS)
const {
369 assert(SrcAS != DestAS &&
"Expected different address spaces!");
372 return SrcAS < 256 && DestAS < 256;
397 return getTM<X86TargetMachine>();
414 void addIRPasses()
override;
415 bool addInstSelector()
override;
416 bool addIRTranslator()
override;
417 bool addLegalizeMachineIR()
override;
418 bool addRegBankSelect()
override;
419 bool addGlobalInstructionSelect()
override;
420 bool addILPOpts()
override;
421 bool addPreISel()
override;
422 void addMachineSSAOptimization()
override;
423 void addPreRegAlloc()
override;
424 bool addPostFastRegAllocRewrite()
override;
425 void addPostRegAlloc()
override;
426 void addPreEmitPass()
override;
427 void addPreEmitPass2()
override;
428 void addPreSched2()
override;
429 bool addRegAssignAndRewriteOptimized()
override;
431 std::unique_ptr<CSEConfigBase> getCSEConfig()
const override;
439 return "X86 Execution Dependency Fix";
442char X86ExecutionDomainFix::ID;
447 "X86 Execution Domain Fix",
false,
false)
453 return new X86PassConfig(*
this, PM);
459 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(
Allocator,
F,
463void X86PassConfig::addIRPasses() {
484 const Triple &TT =
TM->getTargetTriple();
485 if (TT.isOSWindows()) {
493 if (
TM->Options.JMCInstrument)
497bool X86PassConfig::addInstSelector() {
502 if (
TM->getTargetTriple().isOSBinFormatELF() &&
511bool X86PassConfig::addIRTranslator() {
516bool X86PassConfig::addLegalizeMachineIR() {
521bool X86PassConfig::addRegBankSelect() {
526bool X86PassConfig::addGlobalInstructionSelect() {
529 if (isGlobalISelAbortEnabled())
534bool X86PassConfig::addILPOpts() {
542bool X86PassConfig::addPreISel() {
550void X86PassConfig::addPreRegAlloc() {
570void X86PassConfig::addMachineSSAOptimization() {
575void X86PassConfig::addPostRegAlloc() {
586void X86PassConfig::addPreSched2() {
591void X86PassConfig::addPreEmitPass() {
593 addPass(
new X86ExecutionDomainFix());
614void X86PassConfig::addPreEmitPass2() {
639 if (!
TT.isOSDarwin() &&
640 (!
TT.isOSWindows() ||
644 if (
TT.isOSWindows()) {
662 return M->getModuleFlag(
"kcfi") ||
664 (
M->getFunction(
"objc_retainAutoreleasedReturnValue") ||
665 M->getFunction(
"objc_unsafeClaimAutoreleasedReturnValue")));
669bool X86PassConfig::addPostFastRegAllocRewrite() {
674std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig()
const {
685bool X86PassConfig::addRegAssignAndRewriteOptimized() {
unsigned const MachineRegisterInfo * MRI
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static std::string computeDataLayout()
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallString class.
Target-Independent Code Generator Pass Configuration Options pass.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
Allocate memory in an ever growing pool, as if by bump-pointer.
static const char * getManglingComponent(const Triple &T)
Lightweight error class with error context and mandatory checking.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
A Module instance is used to store all the information related to an LLVM module.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Wrapper class representing virtual and physical registers.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
FunctionPass * createX86CompressEVEXPass()
This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86FixupInstTuningPassPass(PassRegistry &)
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeKCFIPass(PassRegistry &)
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
void initializeCompressEVEXPassPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
void initializeX86FixupVectorConstantsPassPass(PassRegistry &)
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86WinFixupBufferSecurityCheckPass()
Return a pass that transform inline buffer security check into seperate bb.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.