LLVM 17.0.0git
X86TargetMachine.cpp
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1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
16#include "X86.h"
17#include "X86CallLowering.h"
18#include "X86LegalizerInfo.h"
20#include "X86MacroFusion.h"
21#include "X86Subtarget.h"
22#include "X86TargetObjectFile.h"
24#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/StringRef.h"
37#include "llvm/CodeGen/Passes.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/Function.h"
43#include "llvm/MC/MCAsmInfo.h"
45#include "llvm/Pass.h"
53#include <memory>
54#include <optional>
55#include <string>
56
57using namespace llvm;
58
59static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
60 cl::desc("Enable the machine combiner pass"),
61 cl::init(true), cl::Hidden);
62
63static cl::opt<bool>
64 EnableTileRAPass("x86-tile-ra",
65 cl::desc("Enable the tile register allocation pass"),
66 cl::init(true), cl::Hidden);
67
69 // Register the target.
72
108}
109
110static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
111 if (TT.isOSBinFormatMachO()) {
112 if (TT.getArch() == Triple::x86_64)
113 return std::make_unique<X86_64MachoTargetObjectFile>();
114 return std::make_unique<TargetLoweringObjectFileMachO>();
115 }
116
117 if (TT.isOSBinFormatCOFF())
118 return std::make_unique<TargetLoweringObjectFileCOFF>();
119 return std::make_unique<X86ELFTargetObjectFile>();
120}
121
122static std::string computeDataLayout(const Triple &TT) {
123 // X86 is little endian
124 std::string Ret = "e";
125
127 // X86 and x32 have 32 bit pointers.
128 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
129 Ret += "-p:32:32";
130
131 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
132 Ret += "-p270:32:32-p271:32:32-p272:64:64";
133
134 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
135 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
136 Ret += "-i64:64";
137 else if (TT.isOSIAMCU())
138 Ret += "-i64:32-f64:32";
139 else
140 Ret += "-f64:32:64";
141
142 // Some ABIs align long double to 128 bits, others to 32.
143 if (TT.isOSNaCl() || TT.isOSIAMCU())
144 ; // No f80
145 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
146 Ret += "-f80:128";
147 else
148 Ret += "-f80:32";
149
150 if (TT.isOSIAMCU())
151 Ret += "-f128:32";
152
153 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
154 if (TT.isArch64Bit())
155 Ret += "-n8:16:32:64";
156 else
157 Ret += "-n8:16:32";
158
159 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
160 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
161 Ret += "-a:0:32-S32";
162 else
163 Ret += "-S128";
164
165 return Ret;
166}
167
168static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
169 std::optional<Reloc::Model> RM) {
170 bool is64Bit = TT.getArch() == Triple::x86_64;
171 if (!RM) {
172 // JIT codegen should use static relocations by default, since it's
173 // typically executed in process and not relocatable.
174 if (JIT)
175 return Reloc::Static;
176
177 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
178 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
179 // use static relocation model by default.
180 if (TT.isOSDarwin()) {
181 if (is64Bit)
182 return Reloc::PIC_;
183 return Reloc::DynamicNoPIC;
184 }
185 if (TT.isOSWindows() && is64Bit)
186 return Reloc::PIC_;
187 return Reloc::Static;
188 }
189
190 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
191 // is defined as a model for code which may be used in static or dynamic
192 // executables but not necessarily a shared library. On X86-32 we just
193 // compile in -static mode, in x86-64 we use PIC.
194 if (*RM == Reloc::DynamicNoPIC) {
195 if (is64Bit)
196 return Reloc::PIC_;
197 if (!TT.isOSDarwin())
198 return Reloc::Static;
199 }
200
201 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
202 // the Mach-O file format doesn't support it.
203 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
204 return Reloc::PIC_;
205
206 return *RM;
207}
208
209static CodeModel::Model
210getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
211 bool Is64Bit) {
212 if (CM) {
213 if (*CM == CodeModel::Tiny)
214 report_fatal_error("Target does not support the tiny CodeModel", false);
215 return *CM;
216 }
217 if (JIT)
218 return Is64Bit ? CodeModel::Large : CodeModel::Small;
219 return CodeModel::Small;
220}
221
222/// Create an X86 target.
223///
225 StringRef CPU, StringRef FS,
226 const TargetOptions &Options,
227 std::optional<Reloc::Model> RM,
228 std::optional<CodeModel::Model> CM,
229 CodeGenOpt::Level OL, bool JIT)
231 T, computeDataLayout(TT), TT, CPU, FS, Options,
232 getEffectiveRelocModel(TT, JIT, RM),
233 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
234 OL),
235 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
236 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
237 // the calling function, and TrapUnreachable is an easy way to get that.
238 if (TT.isPS() || TT.isOSBinFormatMachO()) {
239 this->Options.TrapUnreachable = true;
240 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
241 }
242
243 setMachineOutliner(true);
244
245 // x86 supports the debug entry values.
247
248 initAsmInfo();
249}
250
252
253const X86Subtarget *
255 Attribute CPUAttr = F.getFnAttribute("target-cpu");
256 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
257 Attribute FSAttr = F.getFnAttribute("target-features");
258
259 StringRef CPU =
260 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
261 // "x86-64" is a default target setting for many front ends. In these cases,
262 // they actually request for "generic" tuning unless the "tune-cpu" was
263 // specified.
264 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
265 : CPU == "x86-64" ? "generic"
266 : (StringRef)CPU;
267 StringRef FS =
268 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
269
271 // The additions here are ordered so that the definitely short strings are
272 // added first so we won't exceed the small size. We append the
273 // much longer FS string at the end so that we only heap allocate at most
274 // one time.
275
276 // Extract prefer-vector-width attribute.
277 unsigned PreferVectorWidthOverride = 0;
278 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
279 if (PreferVecWidthAttr.isValid()) {
280 StringRef Val = PreferVecWidthAttr.getValueAsString();
281 unsigned Width;
282 if (!Val.getAsInteger(0, Width)) {
283 Key += 'p';
284 Key += Val;
285 PreferVectorWidthOverride = Width;
286 }
287 }
288
289 // Extract min-legal-vector-width attribute.
290 unsigned RequiredVectorWidth = UINT32_MAX;
291 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
292 if (MinLegalVecWidthAttr.isValid()) {
293 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
294 unsigned Width;
295 if (!Val.getAsInteger(0, Width)) {
296 Key += 'm';
297 Key += Val;
298 RequiredVectorWidth = Width;
299 }
300 }
301
302 // Add CPU to the Key.
303 Key += CPU;
304
305 // Add tune CPU to the Key.
306 Key += TuneCPU;
307
308 // Keep track of the start of the feature portion of the string.
309 unsigned FSStart = Key.size();
310
311 // FIXME: This is related to the code below to reset the target options,
312 // we need to know whether or not the soft float flag is set on the
313 // function before we can generate a subtarget. We also need to use
314 // it as a key for the subtarget since that can be the only difference
315 // between two functions.
316 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
317 // If the soft float attribute is set on the function turn on the soft float
318 // subtarget feature.
319 if (SoftFloat)
320 Key += FS.empty() ? "+soft-float" : "+soft-float,";
321
322 Key += FS;
323
324 // We may have added +soft-float to the features so move the StringRef to
325 // point to the full string in the Key.
326 FS = Key.substr(FSStart);
327
328 auto &I = SubtargetMap[Key];
329 if (!I) {
330 // This needs to be done before we create a new subtarget since any
331 // creation will depend on the TM and the code generation flags on the
332 // function that reside in TargetOptions.
334 I = std::make_unique<X86Subtarget>(
335 TargetTriple, CPU, TuneCPU, FS, *this,
336 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
337 PreferVectorWidthOverride, RequiredVectorWidth);
338 }
339 return I.get();
340}
341
343 unsigned DestAS) const {
344 assert(SrcAS != DestAS && "Expected different address spaces!");
345 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
346 return false;
347 return SrcAS < 256 && DestAS < 256;
348}
349
350//===----------------------------------------------------------------------===//
351// X86 TTI query.
352//===----------------------------------------------------------------------===//
353
356 return TargetTransformInfo(X86TTIImpl(this, F));
357}
358
359//===----------------------------------------------------------------------===//
360// Pass Pipeline Configuration
361//===----------------------------------------------------------------------===//
362
363namespace {
364
365/// X86 Code Generator Pass Configuration Options.
366class X86PassConfig : public TargetPassConfig {
367public:
368 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
369 : TargetPassConfig(TM, PM) {}
370
371 X86TargetMachine &getX86TargetMachine() const {
372 return getTM<X86TargetMachine>();
373 }
374
376 createMachineScheduler(MachineSchedContext *C) const override {
379 return DAG;
380 }
381
383 createPostMachineScheduler(MachineSchedContext *C) const override {
386 return DAG;
387 }
388
389 void addIRPasses() override;
390 bool addInstSelector() override;
391 bool addIRTranslator() override;
392 bool addLegalizeMachineIR() override;
393 bool addRegBankSelect() override;
394 bool addGlobalInstructionSelect() override;
395 bool addILPOpts() override;
396 bool addPreISel() override;
397 void addMachineSSAOptimization() override;
398 void addPreRegAlloc() override;
399 bool addPostFastRegAllocRewrite() override;
400 void addPostRegAlloc() override;
401 void addPreEmitPass() override;
402 void addPreEmitPass2() override;
403 void addPreSched2() override;
404 bool addRegAssignAndRewriteOptimized() override;
405
406 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
407};
408
409class X86ExecutionDomainFix : public ExecutionDomainFix {
410public:
411 static char ID;
412 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
413 StringRef getPassName() const override {
414 return "X86 Execution Dependency Fix";
415 }
416};
417char X86ExecutionDomainFix::ID;
418
419} // end anonymous namespace
420
421INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
422 "X86 Execution Domain Fix", false, false)
424INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
425 "X86 Execution Domain Fix", false, false)
426
428 return new X86PassConfig(*this, PM);
429}
430
432 BumpPtrAllocator &Allocator, const Function &F,
433 const TargetSubtargetInfo *STI) const {
434 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
435 STI);
436}
437
438void X86PassConfig::addIRPasses() {
439 addPass(createAtomicExpandPass());
440
441 // We add both pass anyway and when these two passes run, we skip the pass
442 // based on the option level and option attribute.
444 addPass(createX86LowerAMXTypePass());
445
447
448 if (TM->getOptLevel() != CodeGenOpt::None) {
451 }
452
453 // Add passes that handle indirect branch removal and insertion of a retpoline
454 // thunk. These will be a no-op unless a function subtarget has the retpoline
455 // feature enabled.
457
458 // Add Control Flow Guard checks.
459 const Triple &TT = TM->getTargetTriple();
460 if (TT.isOSWindows()) {
461 if (TT.getArch() == Triple::x86_64) {
462 addPass(createCFGuardDispatchPass());
463 } else {
464 addPass(createCFGuardCheckPass());
465 }
466 }
467
468 if (TM->Options.JMCInstrument)
469 addPass(createJMCInstrumenterPass());
470}
471
472bool X86PassConfig::addInstSelector() {
473 // Install an instruction selector.
474 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
475
476 // For ELF, cleanup any local-dynamic TLS accesses.
477 if (TM->getTargetTriple().isOSBinFormatELF() &&
478 getOptLevel() != CodeGenOpt::None)
480
483 return false;
484}
485
486bool X86PassConfig::addIRTranslator() {
487 addPass(new IRTranslator(getOptLevel()));
488 return false;
489}
490
491bool X86PassConfig::addLegalizeMachineIR() {
492 addPass(new Legalizer());
493 return false;
494}
495
496bool X86PassConfig::addRegBankSelect() {
497 addPass(new RegBankSelect());
498 return false;
499}
500
501bool X86PassConfig::addGlobalInstructionSelect() {
502 addPass(new InstructionSelect(getOptLevel()));
503 return false;
504}
505
506bool X86PassConfig::addILPOpts() {
507 addPass(&EarlyIfConverterID);
509 addPass(&MachineCombinerID);
511 return true;
512}
513
514bool X86PassConfig::addPreISel() {
515 // Only add this pass for 32-bit x86 Windows.
516 const Triple &TT = TM->getTargetTriple();
517 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
518 addPass(createX86WinEHStatePass());
519 return true;
520}
521
522void X86PassConfig::addPreRegAlloc() {
523 if (getOptLevel() != CodeGenOpt::None) {
524 addPass(&LiveRangeShrinkID);
525 addPass(createX86FixupSetCC());
526 addPass(createX86OptimizeLEAs());
529 }
530
534
535 if (getOptLevel() != CodeGenOpt::None)
537 else
539}
540
541void X86PassConfig::addMachineSSAOptimization() {
544}
545
546void X86PassConfig::addPostRegAlloc() {
549 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
550 // to using the Speculative Execution Side Effect Suppression pass for
551 // mitigation. This is to prevent slow downs due to
552 // analyses needed by the LVIHardening pass when compiling at -O0.
553 if (getOptLevel() != CodeGenOpt::None)
555}
556
557void X86PassConfig::addPreSched2() {
558 addPass(createX86ExpandPseudoPass());
559 addPass(createX86KCFIPass());
560}
561
562void X86PassConfig::addPreEmitPass() {
563 if (getOptLevel() != CodeGenOpt::None) {
564 addPass(new X86ExecutionDomainFix());
565 addPass(createBreakFalseDeps());
566 }
567
569
571
572 if (getOptLevel() != CodeGenOpt::None) {
573 addPass(createX86FixupBWInsts());
575 addPass(createX86FixupLEAs());
576 addPass(createX86FixupInstTuning());
577 }
578 addPass(createX86EvexToVexInsts());
582}
583
584void X86PassConfig::addPreEmitPass2() {
585 const Triple &TT = TM->getTargetTriple();
586 const MCAsmInfo *MAI = TM->getMCAsmInfo();
587
588 // The X86 Speculative Execution Pass must run after all control
589 // flow graph modifying passes. As a result it was listed to run right before
590 // the X86 Retpoline Thunks pass. The reason it must run after control flow
591 // graph modifications is that the model of LFENCE in LLVM has to be updated
592 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
593 // placement of this pass was hand checked to ensure that the subsequent
594 // passes don't move the code around the LFENCEs in a way that will hurt the
595 // correctness of this pass. This placement has been shown to work based on
596 // hand inspection of the codegen output.
599 addPass(createX86ReturnThunksPass());
600
601 // Insert extra int3 instructions after trailing call instructions to avoid
602 // issues in the unwinder.
603 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
605
606 // Verify basic block incoming and outgoing cfa offset and register values and
607 // correct CFA calculation rule where needed by inserting appropriate CFI
608 // instructions.
609 if (!TT.isOSDarwin() &&
610 (!TT.isOSWindows() ||
612 addPass(createCFIInstrInserter());
613
614 if (TT.isOSWindows()) {
615 // Identify valid longjmp targets for Windows Control Flow Guard.
616 addPass(createCFGuardLongjmpPass());
617 // Identify valid eh continuation targets for Windows EHCont Guard.
619 }
621
622 // Insert pseudo probe annotation for callsite profiling
623 addPass(createPseudoProbeInserter());
624
625 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
626 // also CALL_RVMARKER.
627 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
628 // Only run bundle expansion if the module uses kcfi, or there are relevant
629 // ObjC runtime functions present in the module.
630 const Function &F = MF.getFunction();
631 const Module *M = F.getParent();
632 return M->getModuleFlag("kcfi") ||
633 (TT.isOSDarwin() &&
634 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
635 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
636 }));
637}
638
639bool X86PassConfig::addPostFastRegAllocRewrite() {
641 return true;
642}
643
644std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
645 return getStandardCSEConfigForOpt(TM->getOptLevel());
646}
647
649 const TargetRegisterClass &RC) {
650 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
651}
652
653bool X86PassConfig::addRegAssignAndRewriteOptimized() {
654 // Don't support tile RA when RA is specified by command line "-regalloc".
655 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
656 // Allocate tile register first.
658 addPass(createX86TileConfigPass());
659 }
661}
Falkor HW Prefetch Fix
arm execution domain fix
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:127
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallString class.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
This file describes how to lower LLVM calls to machine code calls.
static bool is64Bit(const char *name)
This file declares the targeting of the Machinelegalizer class for X86.
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(std::optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:317
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:187
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:149
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:781
Function & getFunction()
Return the LLVM function that this machine code represents.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:468
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
Level
Code generation optimization level.
Definition: CodeGen.h:57
@ DynamicNoPIC
Definition: CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
void initializeX86KCFIPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:311
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:79
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void initializeEvexToVexInstPassPass(PassRegistry &)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:145
FunctionPass * createX86FixupInstTuning()
Return as pass that replaces equivilent slower instructions with faster ones.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
void initializeX86PreAMXConfigPassPass(PassRegistry &)
FunctionPass * createX86KCFIPass()
This pass inserts KCFI checks before indirect calls.
Definition: X86KCFI.cpp:55
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:307
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeX86DAGToDAGISelPass(PassRegistry &)
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
RegisterTargetMachine - Helper template for registering a target machine implementation,...