LLVM 19.0.0git
X86TargetMachine.cpp
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1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
16#include "X86.h"
18#include "X86MacroFusion.h"
19#include "X86Subtarget.h"
20#include "X86TargetObjectFile.h"
22#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringRef.h"
37#include "llvm/CodeGen/Passes.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/DataLayout.h"
42#include "llvm/IR/Function.h"
43#include "llvm/MC/MCAsmInfo.h"
45#include "llvm/Pass.h"
53#include <memory>
54#include <optional>
55#include <string>
56
57using namespace llvm;
58
59static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
60 cl::desc("Enable the machine combiner pass"),
61 cl::init(true), cl::Hidden);
62
63static cl::opt<bool>
64 EnableTileRAPass("x86-tile-ra",
65 cl::desc("Enable the tile register allocation pass"),
66 cl::init(true), cl::Hidden);
67
69 // Register the target.
72
109}
110
111static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
112 if (TT.isOSBinFormatMachO()) {
113 if (TT.getArch() == Triple::x86_64)
114 return std::make_unique<X86_64MachoTargetObjectFile>();
115 return std::make_unique<TargetLoweringObjectFileMachO>();
116 }
117
118 if (TT.isOSBinFormatCOFF())
119 return std::make_unique<TargetLoweringObjectFileCOFF>();
120
121 if (TT.getArch() == Triple::x86_64)
122 return std::make_unique<X86_64ELFTargetObjectFile>();
123 return std::make_unique<X86ELFTargetObjectFile>();
124}
125
126static std::string computeDataLayout(const Triple &TT) {
127 // X86 is little endian
128 std::string Ret = "e";
129
131 // X86 and x32 have 32 bit pointers.
132 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
133 Ret += "-p:32:32";
134
135 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
136 Ret += "-p270:32:32-p271:32:32-p272:64:64";
137
138 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
139 // 128 bit integers are not specified in the 32-bit ABIs but are used
140 // internally for lowering f128, so we match the alignment to that.
141 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
142 Ret += "-i64:64-i128:128";
143 else if (TT.isOSIAMCU())
144 Ret += "-i64:32-f64:32";
145 else
146 Ret += "-i128:128-f64:32:64";
147
148 // Some ABIs align long double to 128 bits, others to 32.
149 if (TT.isOSNaCl() || TT.isOSIAMCU())
150 ; // No f80
151 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
152 Ret += "-f80:128";
153 else
154 Ret += "-f80:32";
155
156 if (TT.isOSIAMCU())
157 Ret += "-f128:32";
158
159 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
160 if (TT.isArch64Bit())
161 Ret += "-n8:16:32:64";
162 else
163 Ret += "-n8:16:32";
164
165 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
166 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
167 Ret += "-a:0:32-S32";
168 else
169 Ret += "-S128";
170
171 return Ret;
172}
173
174static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
175 std::optional<Reloc::Model> RM) {
176 bool is64Bit = TT.getArch() == Triple::x86_64;
177 if (!RM) {
178 // JIT codegen should use static relocations by default, since it's
179 // typically executed in process and not relocatable.
180 if (JIT)
181 return Reloc::Static;
182
183 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
184 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
185 // use static relocation model by default.
186 if (TT.isOSDarwin()) {
187 if (is64Bit)
188 return Reloc::PIC_;
189 return Reloc::DynamicNoPIC;
190 }
191 if (TT.isOSWindows() && is64Bit)
192 return Reloc::PIC_;
193 return Reloc::Static;
194 }
195
196 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
197 // is defined as a model for code which may be used in static or dynamic
198 // executables but not necessarily a shared library. On X86-32 we just
199 // compile in -static mode, in x86-64 we use PIC.
200 if (*RM == Reloc::DynamicNoPIC) {
201 if (is64Bit)
202 return Reloc::PIC_;
203 if (!TT.isOSDarwin())
204 return Reloc::Static;
205 }
206
207 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
208 // the Mach-O file format doesn't support it.
209 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
210 return Reloc::PIC_;
211
212 return *RM;
213}
214
215static CodeModel::Model
216getEffectiveX86CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
217 bool JIT) {
218 bool Is64Bit = TT.getArch() == Triple::x86_64;
219 if (CM) {
220 if (*CM == CodeModel::Tiny)
221 report_fatal_error("Target does not support the tiny CodeModel", false);
222 return *CM;
223 }
224 if (JIT)
225 return Is64Bit ? CodeModel::Large : CodeModel::Small;
226 return CodeModel::Small;
227}
228
229/// Create an X86 target.
230///
232 StringRef CPU, StringRef FS,
233 const TargetOptions &Options,
234 std::optional<Reloc::Model> RM,
235 std::optional<CodeModel::Model> CM,
236 CodeGenOptLevel OL, bool JIT)
238 T, computeDataLayout(TT), TT, CPU, FS, Options,
239 getEffectiveRelocModel(TT, JIT, RM),
240 getEffectiveX86CodeModel(TT, CM, JIT),
241 OL),
242 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
243 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
244 // the calling function, and TrapUnreachable is an easy way to get that.
245 if (TT.isPS() || TT.isOSBinFormatMachO()) {
246 this->Options.TrapUnreachable = true;
247 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
248 }
249
250 setMachineOutliner(true);
251
252 // x86 supports the debug entry values.
254
255 initAsmInfo();
256}
257
259
260const X86Subtarget *
262 Attribute CPUAttr = F.getFnAttribute("target-cpu");
263 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
264 Attribute FSAttr = F.getFnAttribute("target-features");
265
266 StringRef CPU =
267 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
268 // "x86-64" is a default target setting for many front ends. In these cases,
269 // they actually request for "generic" tuning unless the "tune-cpu" was
270 // specified.
271 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
272 : CPU == "x86-64" ? "generic"
273 : (StringRef)CPU;
274 StringRef FS =
275 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
276
278 // The additions here are ordered so that the definitely short strings are
279 // added first so we won't exceed the small size. We append the
280 // much longer FS string at the end so that we only heap allocate at most
281 // one time.
282
283 // Extract prefer-vector-width attribute.
284 unsigned PreferVectorWidthOverride = 0;
285 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
286 if (PreferVecWidthAttr.isValid()) {
287 StringRef Val = PreferVecWidthAttr.getValueAsString();
288 unsigned Width;
289 if (!Val.getAsInteger(0, Width)) {
290 Key += 'p';
291 Key += Val;
292 PreferVectorWidthOverride = Width;
293 }
294 }
295
296 // Extract min-legal-vector-width attribute.
297 unsigned RequiredVectorWidth = UINT32_MAX;
298 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
299 if (MinLegalVecWidthAttr.isValid()) {
300 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
301 unsigned Width;
302 if (!Val.getAsInteger(0, Width)) {
303 Key += 'm';
304 Key += Val;
305 RequiredVectorWidth = Width;
306 }
307 }
308
309 // Add CPU to the Key.
310 Key += CPU;
311
312 // Add tune CPU to the Key.
313 Key += TuneCPU;
314
315 // Keep track of the start of the feature portion of the string.
316 unsigned FSStart = Key.size();
317
318 // FIXME: This is related to the code below to reset the target options,
319 // we need to know whether or not the soft float flag is set on the
320 // function before we can generate a subtarget. We also need to use
321 // it as a key for the subtarget since that can be the only difference
322 // between two functions.
323 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
324 // If the soft float attribute is set on the function turn on the soft float
325 // subtarget feature.
326 if (SoftFloat)
327 Key += FS.empty() ? "+soft-float" : "+soft-float,";
328
329 Key += FS;
330
331 // We may have added +soft-float to the features so move the StringRef to
332 // point to the full string in the Key.
333 FS = Key.substr(FSStart);
334
335 auto &I = SubtargetMap[Key];
336 if (!I) {
337 // This needs to be done before we create a new subtarget since any
338 // creation will depend on the TM and the code generation flags on the
339 // function that reside in TargetOptions.
341 I = std::make_unique<X86Subtarget>(
342 TargetTriple, CPU, TuneCPU, FS, *this,
343 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
344 PreferVectorWidthOverride, RequiredVectorWidth);
345 }
346 return I.get();
347}
348
350 return new yaml::X86MachineFunctionInfo();
351}
352
355 const auto *MFI = MF.getInfo<X86MachineFunctionInfo>();
356 return new yaml::X86MachineFunctionInfo(*MFI);
357}
358
361 SMDiagnostic &Error, SMRange &SourceRange) const {
362 const auto &YamlMFI = static_cast<const yaml::X86MachineFunctionInfo &>(MFI);
363 PFS.MF.getInfo<X86MachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
364 return false;
365}
366
368 unsigned DestAS) const {
369 assert(SrcAS != DestAS && "Expected different address spaces!");
370 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
371 return false;
372 return SrcAS < 256 && DestAS < 256;
373}
374
375//===----------------------------------------------------------------------===//
376// X86 TTI query.
377//===----------------------------------------------------------------------===//
378
381 return TargetTransformInfo(X86TTIImpl(this, F));
382}
383
384//===----------------------------------------------------------------------===//
385// Pass Pipeline Configuration
386//===----------------------------------------------------------------------===//
387
388namespace {
389
390/// X86 Code Generator Pass Configuration Options.
391class X86PassConfig : public TargetPassConfig {
392public:
393 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
394 : TargetPassConfig(TM, PM) {}
395
396 X86TargetMachine &getX86TargetMachine() const {
397 return getTM<X86TargetMachine>();
398 }
399
401 createMachineScheduler(MachineSchedContext *C) const override {
404 return DAG;
405 }
406
408 createPostMachineScheduler(MachineSchedContext *C) const override {
411 return DAG;
412 }
413
414 void addIRPasses() override;
415 bool addInstSelector() override;
416 bool addIRTranslator() override;
417 bool addLegalizeMachineIR() override;
418 bool addRegBankSelect() override;
419 bool addGlobalInstructionSelect() override;
420 bool addILPOpts() override;
421 bool addPreISel() override;
422 void addMachineSSAOptimization() override;
423 void addPreRegAlloc() override;
424 bool addPostFastRegAllocRewrite() override;
425 void addPostRegAlloc() override;
426 void addPreEmitPass() override;
427 void addPreEmitPass2() override;
428 void addPreSched2() override;
429 bool addRegAssignAndRewriteOptimized() override;
430
431 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
432};
433
434class X86ExecutionDomainFix : public ExecutionDomainFix {
435public:
436 static char ID;
437 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
438 StringRef getPassName() const override {
439 return "X86 Execution Dependency Fix";
440 }
441};
442char X86ExecutionDomainFix::ID;
443
444} // end anonymous namespace
445
446INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
447 "X86 Execution Domain Fix", false, false)
449INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
450 "X86 Execution Domain Fix", false, false)
451
453 return new X86PassConfig(*this, PM);
454}
455
457 BumpPtrAllocator &Allocator, const Function &F,
458 const TargetSubtargetInfo *STI) const {
459 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
460 STI);
461}
462
463void X86PassConfig::addIRPasses() {
465
466 // We add both pass anyway and when these two passes run, we skip the pass
467 // based on the option level and option attribute.
469 addPass(createX86LowerAMXTypePass());
470
472
473 if (TM->getOptLevel() != CodeGenOptLevel::None) {
476 }
477
478 // Add passes that handle indirect branch removal and insertion of a retpoline
479 // thunk. These will be a no-op unless a function subtarget has the retpoline
480 // feature enabled.
482
483 // Add Control Flow Guard checks.
484 const Triple &TT = TM->getTargetTriple();
485 if (TT.isOSWindows()) {
486 if (TT.getArch() == Triple::x86_64) {
487 addPass(createCFGuardDispatchPass());
488 } else {
489 addPass(createCFGuardCheckPass());
490 }
491 }
492
493 if (TM->Options.JMCInstrument)
494 addPass(createJMCInstrumenterPass());
495}
496
497bool X86PassConfig::addInstSelector() {
498 // Install an instruction selector.
499 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
500
501 // For ELF, cleanup any local-dynamic TLS accesses.
502 if (TM->getTargetTriple().isOSBinFormatELF() &&
503 getOptLevel() != CodeGenOptLevel::None)
505
508 return false;
509}
510
511bool X86PassConfig::addIRTranslator() {
512 addPass(new IRTranslator(getOptLevel()));
513 return false;
514}
515
516bool X86PassConfig::addLegalizeMachineIR() {
517 addPass(new Legalizer());
518 return false;
519}
520
521bool X86PassConfig::addRegBankSelect() {
522 addPass(new RegBankSelect());
523 return false;
524}
525
526bool X86PassConfig::addGlobalInstructionSelect() {
527 addPass(new InstructionSelect(getOptLevel()));
528 // Add GlobalBaseReg in case there is no SelectionDAG passes afterwards
529 if (isGlobalISelAbortEnabled())
531 return false;
532}
533
534bool X86PassConfig::addILPOpts() {
535 addPass(&EarlyIfConverterID);
537 addPass(&MachineCombinerID);
539 return true;
540}
541
542bool X86PassConfig::addPreISel() {
543 // Only add this pass for 32-bit x86 Windows.
544 const Triple &TT = TM->getTargetTriple();
545 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
546 addPass(createX86WinEHStatePass());
547 return true;
548}
549
550void X86PassConfig::addPreRegAlloc() {
551 if (getOptLevel() != CodeGenOptLevel::None) {
552 addPass(&LiveRangeShrinkID);
553 addPass(createX86FixupSetCC());
554 addPass(createX86OptimizeLEAs());
557 }
558
562
563 if (getOptLevel() != CodeGenOptLevel::None)
565 else
567}
568
569void X86PassConfig::addMachineSSAOptimization() {
572}
573
574void X86PassConfig::addPostRegAlloc() {
577 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
578 // to using the Speculative Execution Side Effect Suppression pass for
579 // mitigation. This is to prevent slow downs due to
580 // analyses needed by the LVIHardening pass when compiling at -O0.
581 if (getOptLevel() != CodeGenOptLevel::None)
583}
584
585void X86PassConfig::addPreSched2() {
586 addPass(createX86ExpandPseudoPass());
587 addPass(createKCFIPass());
588}
589
590void X86PassConfig::addPreEmitPass() {
591 if (getOptLevel() != CodeGenOptLevel::None) {
592 addPass(new X86ExecutionDomainFix());
593 addPass(createBreakFalseDeps());
594 }
595
597
599
600 if (getOptLevel() != CodeGenOptLevel::None) {
601 addPass(createX86FixupBWInsts());
603 addPass(createX86FixupLEAs());
604 addPass(createX86FixupInstTuning());
606 }
607 addPass(createX86CompressEVEXPass());
611}
612
613void X86PassConfig::addPreEmitPass2() {
614 const Triple &TT = TM->getTargetTriple();
615 const MCAsmInfo *MAI = TM->getMCAsmInfo();
616
617 // The X86 Speculative Execution Pass must run after all control
618 // flow graph modifying passes. As a result it was listed to run right before
619 // the X86 Retpoline Thunks pass. The reason it must run after control flow
620 // graph modifications is that the model of LFENCE in LLVM has to be updated
621 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
622 // placement of this pass was hand checked to ensure that the subsequent
623 // passes don't move the code around the LFENCEs in a way that will hurt the
624 // correctness of this pass. This placement has been shown to work based on
625 // hand inspection of the codegen output.
628 addPass(createX86ReturnThunksPass());
629
630 // Insert extra int3 instructions after trailing call instructions to avoid
631 // issues in the unwinder.
632 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
634
635 // Verify basic block incoming and outgoing cfa offset and register values and
636 // correct CFA calculation rule where needed by inserting appropriate CFI
637 // instructions.
638 if (!TT.isOSDarwin() &&
639 (!TT.isOSWindows() ||
641 addPass(createCFIInstrInserter());
642
643 if (TT.isOSWindows()) {
644 // Identify valid longjmp targets for Windows Control Flow Guard.
645 addPass(createCFGuardLongjmpPass());
646 // Identify valid eh continuation targets for Windows EHCont Guard.
648 }
650
651 // Insert pseudo probe annotation for callsite profiling
652 addPass(createPseudoProbeInserter());
653
654 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
655 // also CALL_RVMARKER.
656 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
657 // Only run bundle expansion if the module uses kcfi, or there are relevant
658 // ObjC runtime functions present in the module.
659 const Function &F = MF.getFunction();
660 const Module *M = F.getParent();
661 return M->getModuleFlag("kcfi") ||
662 (TT.isOSDarwin() &&
663 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
664 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
665 }));
666}
667
668bool X86PassConfig::addPostFastRegAllocRewrite() {
670 return true;
671}
672
673std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
674 return getStandardCSEConfigForOpt(TM->getOptLevel());
675}
676
678 const TargetRegisterClass &RC) {
679 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
680}
681
682bool X86PassConfig::addRegAssignAndRewriteOptimized() {
683 // Don't support tile RA when RA is specified by command line "-regalloc".
684 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
685 // Allocate tile register first.
687 addPass(createX86TileConfigPass());
688 }
690}
Falkor HW Prefetch Fix
arm execution domain fix
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallString class.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:349
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:193
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:780
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Definition: SourceMgr.h:281
Represents a range in source code.
Definition: SMLoc.h:48
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:463
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:95
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
Definition: TargetMachine.h:97
std::string TargetCPU
Definition: TargetMachine.h:96
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:317
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
FunctionPass * createX86CompressEVEXPass()
This pass compress instructions from EVEX space to legacy/VEX/EVEX space when possible in order to re...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:167
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86FixupInstTuningPassPass(PassRegistry &)
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeKCFIPass(PassRegistry &)
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
void initializeCompressEVEXPassPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:313
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
void initializeX86FixupVectorConstantsPassPass(PassRegistry &)
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.