LLVM  12.0.0git
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
36 #include "llvm/CodeGen/Passes.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56  cl::desc("Enable the machine combiner pass"),
57  cl::init(true), cl::Hidden);
58 
60  // Register the target.
63 
89 }
90 
91 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
92  if (TT.isOSBinFormatMachO()) {
93  if (TT.getArch() == Triple::x86_64)
94  return std::make_unique<X86_64MachoTargetObjectFile>();
95  return std::make_unique<TargetLoweringObjectFileMachO>();
96  }
97 
98  if (TT.isOSBinFormatCOFF())
99  return std::make_unique<TargetLoweringObjectFileCOFF>();
100  return std::make_unique<X86ELFTargetObjectFile>();
101 }
102 
103 static std::string computeDataLayout(const Triple &TT) {
104  // X86 is little endian
105  std::string Ret = "e";
106 
108  // X86 and x32 have 32 bit pointers.
109  if ((TT.isArch64Bit() &&
110  (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
111  !TT.isArch64Bit())
112  Ret += "-p:32:32";
113 
114  // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
115  Ret += "-p270:32:32-p271:32:32-p272:64:64";
116 
117  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
118  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
119  Ret += "-i64:64";
120  else if (TT.isOSIAMCU())
121  Ret += "-i64:32-f64:32";
122  else
123  Ret += "-f64:32:64";
124 
125  // Some ABIs align long double to 128 bits, others to 32.
126  if (TT.isOSNaCl() || TT.isOSIAMCU())
127  ; // No f80
128  else if (TT.isArch64Bit() || TT.isOSDarwin())
129  Ret += "-f80:128";
130  else
131  Ret += "-f80:32";
132 
133  if (TT.isOSIAMCU())
134  Ret += "-f128:32";
135 
136  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
137  if (TT.isArch64Bit())
138  Ret += "-n8:16:32:64";
139  else
140  Ret += "-n8:16:32";
141 
142  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
143  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
144  Ret += "-a:0:32-S32";
145  else
146  Ret += "-S128";
147 
148  return Ret;
149 }
150 
152  bool JIT,
154  bool is64Bit = TT.getArch() == Triple::x86_64;
155  if (!RM.hasValue()) {
156  // JIT codegen should use static relocations by default, since it's
157  // typically executed in process and not relocatable.
158  if (JIT)
159  return Reloc::Static;
160 
161  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
162  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
163  // use static relocation model by default.
164  if (TT.isOSDarwin()) {
165  if (is64Bit)
166  return Reloc::PIC_;
167  return Reloc::DynamicNoPIC;
168  }
169  if (TT.isOSWindows() && is64Bit)
170  return Reloc::PIC_;
171  return Reloc::Static;
172  }
173 
174  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
175  // is defined as a model for code which may be used in static or dynamic
176  // executables but not necessarily a shared library. On X86-32 we just
177  // compile in -static mode, in x86-64 we use PIC.
178  if (*RM == Reloc::DynamicNoPIC) {
179  if (is64Bit)
180  return Reloc::PIC_;
181  if (!TT.isOSDarwin())
182  return Reloc::Static;
183  }
184 
185  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
186  // the Mach-O file format doesn't support it.
187  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
188  return Reloc::PIC_;
189 
190  return *RM;
191 }
192 
194  bool JIT, bool Is64Bit) {
195  if (CM) {
196  if (*CM == CodeModel::Tiny)
197  report_fatal_error("Target does not support the tiny CodeModel", false);
198  return *CM;
199  }
200  if (JIT)
201  return Is64Bit ? CodeModel::Large : CodeModel::Small;
202  return CodeModel::Small;
203 }
204 
205 /// Create an X86 target.
206 ///
208  StringRef CPU, StringRef FS,
209  const TargetOptions &Options,
212  CodeGenOpt::Level OL, bool JIT)
214  T, computeDataLayout(TT), TT, CPU, FS, Options,
216  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
217  OL),
218  TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
219  // On PS4, the "return address" of a 'noreturn' call must still be within
220  // the calling function, and TrapUnreachable is an easy way to get that.
221  if (TT.isPS4() || TT.isOSBinFormatMachO()) {
222  this->Options.TrapUnreachable = true;
223  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
224  }
225 
226  setMachineOutliner(true);
227 
228  // x86 supports the debug entry values.
230 
231  initAsmInfo();
232 }
233 
235 
236 const X86Subtarget *
238  Attribute CPUAttr = F.getFnAttribute("target-cpu");
239  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
240  Attribute FSAttr = F.getFnAttribute("target-features");
241 
242  StringRef CPU =
243  CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
244  StringRef TuneCPU =
245  TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
246  StringRef FS =
247  FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
248 
250  // The additions here are ordered so that the definitely short strings are
251  // added first so we won't exceed the small size. We append the
252  // much longer FS string at the end so that we only heap allocate at most
253  // one time.
254 
255  // Extract prefer-vector-width attribute.
256  unsigned PreferVectorWidthOverride = 0;
257  Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
258  if (PreferVecWidthAttr.isValid()) {
259  StringRef Val = PreferVecWidthAttr.getValueAsString();
260  unsigned Width;
261  if (!Val.getAsInteger(0, Width)) {
262  Key += "prefer-vector-width=";
263  Key += Val;
264  PreferVectorWidthOverride = Width;
265  }
266  }
267 
268  // Extract min-legal-vector-width attribute.
269  unsigned RequiredVectorWidth = UINT32_MAX;
270  Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
271  if (MinLegalVecWidthAttr.isValid()) {
272  StringRef Val = MinLegalVecWidthAttr.getValueAsString();
273  unsigned Width;
274  if (!Val.getAsInteger(0, Width)) {
275  Key += "min-legal-vector-width=";
276  Key += Val;
277  RequiredVectorWidth = Width;
278  }
279  }
280 
281  // Add CPU to the Key.
282  Key += CPU;
283 
284  // Add tune CPU to the Key.
285  Key += "tune=";
286  Key += TuneCPU;
287 
288  // Keep track of the start of the feature portion of the string.
289  unsigned FSStart = Key.size();
290 
291  // FIXME: This is related to the code below to reset the target options,
292  // we need to know whether or not the soft float flag is set on the
293  // function before we can generate a subtarget. We also need to use
294  // it as a key for the subtarget since that can be the only difference
295  // between two functions.
296  bool SoftFloat =
297  F.getFnAttribute("use-soft-float").getValueAsString() == "true";
298  // If the soft float attribute is set on the function turn on the soft float
299  // subtarget feature.
300  if (SoftFloat)
301  Key += FS.empty() ? "+soft-float" : "+soft-float,";
302 
303  Key += FS;
304 
305  // We may have added +soft-float to the features so move the StringRef to
306  // point to the full string in the Key.
307  FS = Key.substr(FSStart);
308 
309  auto &I = SubtargetMap[Key];
310  if (!I) {
311  // This needs to be done before we create a new subtarget since any
312  // creation will depend on the TM and the code generation flags on the
313  // function that reside in TargetOptions.
315  I = std::make_unique<X86Subtarget>(
316  TargetTriple, CPU, TuneCPU, FS, *this,
317  MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
318  RequiredVectorWidth);
319  }
320  return I.get();
321 }
322 
324  unsigned DestAS) const {
325  assert(SrcAS != DestAS && "Expected different address spaces!");
326  if (getPointerSize(SrcAS) != getPointerSize(DestAS))
327  return false;
328  return SrcAS < 256 && DestAS < 256;
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // X86 TTI query.
333 //===----------------------------------------------------------------------===//
334 
337  return TargetTransformInfo(X86TTIImpl(this, F));
338 }
339 
340 //===----------------------------------------------------------------------===//
341 // Pass Pipeline Configuration
342 //===----------------------------------------------------------------------===//
343 
344 namespace {
345 
346 /// X86 Code Generator Pass Configuration Options.
347 class X86PassConfig : public TargetPassConfig {
348 public:
349  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
350  : TargetPassConfig(TM, PM) {}
351 
352  X86TargetMachine &getX86TargetMachine() const {
353  return getTM<X86TargetMachine>();
354  }
355 
357  createMachineScheduler(MachineSchedContext *C) const override {
360  return DAG;
361  }
362 
364  createPostMachineScheduler(MachineSchedContext *C) const override {
367  return DAG;
368  }
369 
370  void addIRPasses() override;
371  bool addInstSelector() override;
372  bool addIRTranslator() override;
373  bool addLegalizeMachineIR() override;
374  bool addRegBankSelect() override;
375  bool addGlobalInstructionSelect() override;
376  bool addILPOpts() override;
377  bool addPreISel() override;
378  void addMachineSSAOptimization() override;
379  void addPreRegAlloc() override;
380  void addPostRegAlloc() override;
381  void addPreEmitPass() override;
382  void addPreEmitPass2() override;
383  void addPreSched2() override;
384  bool addPreRewrite() override;
385 
386  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
387 };
388 
389 class X86ExecutionDomainFix : public ExecutionDomainFix {
390 public:
391  static char ID;
392  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
393  StringRef getPassName() const override {
394  return "X86 Execution Dependency Fix";
395  }
396 };
398 
399 } // end anonymous namespace
400 
401 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
402  "X86 Execution Domain Fix", false, false)
404 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
405  "X86 Execution Domain Fix", false, false)
406 
408  return new X86PassConfig(*this, PM);
409 }
410 
411 void X86PassConfig::addIRPasses() {
412  addPass(createAtomicExpandPass());
413  addPass(createX86LowerAMXTypePass());
414 
416 
417  if (TM->getOptLevel() != CodeGenOpt::None) {
418  addPass(createInterleavedAccessPass());
420  }
421 
422  // Add passes that handle indirect branch removal and insertion of a retpoline
423  // thunk. These will be a no-op unless a function subtarget has the retpoline
424  // feature enabled.
425  addPass(createIndirectBrExpandPass());
426 
427  // Add Control Flow Guard checks.
428  const Triple &TT = TM->getTargetTriple();
429  if (TT.isOSWindows()) {
430  if (TT.getArch() == Triple::x86_64) {
431  addPass(createCFGuardDispatchPass());
432  } else {
433  addPass(createCFGuardCheckPass());
434  }
435  }
436 }
437 
438 bool X86PassConfig::addInstSelector() {
439  // Install an instruction selector.
440  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
441 
442  // For ELF, cleanup any local-dynamic TLS accesses.
443  if (TM->getTargetTriple().isOSBinFormatELF() &&
444  getOptLevel() != CodeGenOpt::None)
446 
447  addPass(createX86GlobalBaseRegPass());
448  return false;
449 }
450 
451 bool X86PassConfig::addIRTranslator() {
452  addPass(new IRTranslator(getOptLevel()));
453  return false;
454 }
455 
456 bool X86PassConfig::addLegalizeMachineIR() {
457  addPass(new Legalizer());
458  return false;
459 }
460 
461 bool X86PassConfig::addRegBankSelect() {
462  addPass(new RegBankSelect());
463  return false;
464 }
465 
466 bool X86PassConfig::addGlobalInstructionSelect() {
467  addPass(new InstructionSelect());
468  return false;
469 }
470 
471 bool X86PassConfig::addILPOpts() {
472  addPass(&EarlyIfConverterID);
474  addPass(&MachineCombinerID);
475  addPass(createX86CmovConverterPass());
476  return true;
477 }
478 
479 bool X86PassConfig::addPreISel() {
480  // Only add this pass for 32-bit x86 Windows.
481  const Triple &TT = TM->getTargetTriple();
482  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
483  addPass(createX86WinEHStatePass());
484  return true;
485 }
486 
487 void X86PassConfig::addPreRegAlloc() {
488  if (getOptLevel() != CodeGenOpt::None) {
489  addPass(&LiveRangeShrinkID);
490  addPass(createX86FixupSetCC());
491  addPass(createX86OptimizeLEAs());
494  }
495 
498  addPass(createX86WinAllocaExpander());
499 
500  if (getOptLevel() != CodeGenOpt::None) {
501  addPass(createX86PreTileConfigPass());
502  }
503 }
504 
505 void X86PassConfig::addMachineSSAOptimization() {
508 }
509 
510 void X86PassConfig::addPostRegAlloc() {
512  // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
513  // to using the Speculative Execution Side Effect Suppression pass for
514  // mitigation. This is to prevent slow downs due to
515  // analyses needed by the LVIHardening pass when compiling at -O0.
516  if (getOptLevel() != CodeGenOpt::None)
518 }
519 
520 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
521 
522 void X86PassConfig::addPreEmitPass() {
523  if (getOptLevel() != CodeGenOpt::None) {
524  addPass(new X86ExecutionDomainFix());
525  addPass(createBreakFalseDeps());
526  }
527 
529 
530  addPass(createX86IssueVZeroUpperPass());
531 
532  if (getOptLevel() != CodeGenOpt::None) {
533  addPass(createX86FixupBWInsts());
534  addPass(createX86PadShortFunctions());
535  addPass(createX86FixupLEAs());
536  }
537  addPass(createX86EvexToVexInsts());
539  addPass(createX86InsertPrefetchPass());
540  addPass(createX86InsertX87waitPass());
541 }
542 
543 void X86PassConfig::addPreEmitPass2() {
544  const Triple &TT = TM->getTargetTriple();
545  const MCAsmInfo *MAI = TM->getMCAsmInfo();
546 
547  // The X86 Speculative Execution Pass must run after all control
548  // flow graph modifying passes. As a result it was listed to run right before
549  // the X86 Retpoline Thunks pass. The reason it must run after control flow
550  // graph modifications is that the model of LFENCE in LLVM has to be updated
551  // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
552  // placement of this pass was hand checked to ensure that the subsequent
553  // passes don't move the code around the LFENCEs in a way that will hurt the
554  // correctness of this pass. This placement has been shown to work based on
555  // hand inspection of the codegen output.
557  addPass(createX86IndirectThunksPass());
558 
559  // Insert extra int3 instructions after trailing call instructions to avoid
560  // issues in the unwinder.
561  if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
563 
564  // Verify basic block incoming and outgoing cfa offset and register values and
565  // correct CFA calculation rule where needed by inserting appropriate CFI
566  // instructions.
567  if (!TT.isOSDarwin() &&
568  (!TT.isOSWindows() ||
570  addPass(createCFIInstrInserter());
571  // Identify valid longjmp targets for Windows Control Flow Guard.
572  if (TT.isOSWindows())
573  addPass(createCFGuardLongjmpPass());
575 }
576 
577 bool X86PassConfig::addPreRewrite() {
578  addPass(createX86TileConfigPass());
579  return true;
580 }
581 
582 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
583  return getStandardCSEConfigForOpt(TM->getOptLevel());
584 }
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
uint64_t CallInst * C
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:294
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:140
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
static std::string computeDataLayout(const Triple &TT)
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:298
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86CallFrameOptimizationPass(PassRegistry &)
F(f)
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
void initializeX86PartialReductionPass(PassRegistry &)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:152
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
void initializeX86CmovConverterPassPass(PassRegistry &)
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
This class provides the reaching def analysis.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
This file contains the simple types necessary to represent the attributes associated with functions a...
void initializeX86FixupSetCCPassPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
void initializeX86AvoidSFBPassPass(PassRegistry &)
Key
PAL metadata keys.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
void initializeEvexToVexInstPassPass(PassRegistry &)
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:25
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:511
speculative execution
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:151
char & LiveRangeShrinkID
LiveRangeShrink pass.
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:73
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
void initializeX86ExecutionDomainFixPass(PassRegistry &)
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
const X86Subtarget * getSubtargetImpl() const =delete
void initializeFixupLEAPassPass(PassRegistry &)
void initializeX86ExpandPseudoPass(PassRegistry &)
This class describes a target machine that is implemented with the LLVM target-independent code gener...
void setMachineOutliner(bool Enable)
x86 execution domain fix
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
FunctionPass * createX86TileConfigPass()
INITIALIZE_PASS_END(RegBankSelect, DEBUG_TYPE, "Assign register bank of generic virtual registers", false, false) RegBankSelect
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
void initializeX86DomainReassignmentPass(PassRegistry &)
Windows x64, Windows Itanium (IA-64)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:45
FunctionPass * createIndirectBrExpandPass()
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:119
FunctionPass * createX86PreTileConfigPass()
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
x86 execution domain X86 Execution Domain Fix
unsigned StackAlignmentOverride
StackAlignmentOverride - Override default stack alignment for target.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:131
FunctionPass * createX86SpeculativeLoadHardeningPass()
This pass is responsible for selecting generic machine instructions to target-specific instructions.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
Target - Wrapper for Target specific information.
This file describes how to lower LLVM calls to machine code calls.
std::string TargetCPU
Definition: TargetMachine.h:97
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86WinAllocaExpander()
Return a pass that expands WinAlloca pseudo-instructions.
void initializeX86OptimizeLEAPassPass(PassRegistry &)
A ScheduleDAG for scheduling lists of MachineInstr.
FunctionPass * createX86LowerAMXTypePass()
The pass transform load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128 ...
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:275
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
TargetOptions Options
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:59
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
Target & getTheX86_32Target()
std::string TargetFS
Definition: TargetMachine.h:98
void initializeWinEHStatePassPass(PassRegistry &)
This file declares the IRTranslator pass.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
This file describes how to lower LLVM calls to machine code calls.
This file declares the targeting of the Machinelegalizer class for X86.
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:639
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:57
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
void setSupportsDebugEntryValues(bool Enable)
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
This pass exposes codegen information to IR-level passes.
DWARF-like instruction based exceptions.
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
FunctionPass * createAtomicExpandPass()
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
Target & getTheX86_64Target()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
static bool is64Bit(const char *name)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)