LLVM 18.0.0git
X86TargetMachine.cpp
Go to the documentation of this file.
1//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86 specific subclass of TargetMachine.
10//
11//===----------------------------------------------------------------------===//
12
13#include "X86TargetMachine.h"
16#include "X86.h"
18#include "X86MacroFusion.h"
19#include "X86Subtarget.h"
20#include "X86TargetObjectFile.h"
22#include "llvm/ADT/STLExtras.h"
24#include "llvm/ADT/StringRef.h"
35#include "llvm/CodeGen/Passes.h"
38#include "llvm/IR/Attributes.h"
39#include "llvm/IR/DataLayout.h"
40#include "llvm/IR/Function.h"
41#include "llvm/MC/MCAsmInfo.h"
43#include "llvm/Pass.h"
51#include <memory>
52#include <optional>
53#include <string>
54
55using namespace llvm;
56
57static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58 cl::desc("Enable the machine combiner pass"),
59 cl::init(true), cl::Hidden);
60
61static cl::opt<bool>
62 EnableTileRAPass("x86-tile-ra",
63 cl::desc("Enable the tile register allocation pass"),
64 cl::init(true), cl::Hidden);
65
67 // Register the target.
70
105}
106
107static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
108 if (TT.isOSBinFormatMachO()) {
109 if (TT.getArch() == Triple::x86_64)
110 return std::make_unique<X86_64MachoTargetObjectFile>();
111 return std::make_unique<TargetLoweringObjectFileMachO>();
112 }
113
114 if (TT.isOSBinFormatCOFF())
115 return std::make_unique<TargetLoweringObjectFileCOFF>();
116 return std::make_unique<X86ELFTargetObjectFile>();
117}
118
119static std::string computeDataLayout(const Triple &TT) {
120 // X86 is little endian
121 std::string Ret = "e";
122
124 // X86 and x32 have 32 bit pointers.
125 if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
126 Ret += "-p:32:32";
127
128 // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
129 Ret += "-p270:32:32-p271:32:32-p272:64:64";
130
131 // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
132 // 128 bit integers are not specified in the 32-bit ABIs but are used
133 // internally for lowering f128, so we match the alignment to that.
134 if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
135 Ret += "-i64:64-i128:128";
136 else if (TT.isOSIAMCU())
137 Ret += "-i64:32-f64:32";
138 else
139 Ret += "-i128:128-f64:32:64";
140
141 // Some ABIs align long double to 128 bits, others to 32.
142 if (TT.isOSNaCl() || TT.isOSIAMCU())
143 ; // No f80
144 else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
145 Ret += "-f80:128";
146 else
147 Ret += "-f80:32";
148
149 if (TT.isOSIAMCU())
150 Ret += "-f128:32";
151
152 // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
153 if (TT.isArch64Bit())
154 Ret += "-n8:16:32:64";
155 else
156 Ret += "-n8:16:32";
157
158 // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
159 if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
160 Ret += "-a:0:32-S32";
161 else
162 Ret += "-S128";
163
164 return Ret;
165}
166
167static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
168 std::optional<Reloc::Model> RM) {
169 bool is64Bit = TT.getArch() == Triple::x86_64;
170 if (!RM) {
171 // JIT codegen should use static relocations by default, since it's
172 // typically executed in process and not relocatable.
173 if (JIT)
174 return Reloc::Static;
175
176 // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
177 // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
178 // use static relocation model by default.
179 if (TT.isOSDarwin()) {
180 if (is64Bit)
181 return Reloc::PIC_;
182 return Reloc::DynamicNoPIC;
183 }
184 if (TT.isOSWindows() && is64Bit)
185 return Reloc::PIC_;
186 return Reloc::Static;
187 }
188
189 // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
190 // is defined as a model for code which may be used in static or dynamic
191 // executables but not necessarily a shared library. On X86-32 we just
192 // compile in -static mode, in x86-64 we use PIC.
193 if (*RM == Reloc::DynamicNoPIC) {
194 if (is64Bit)
195 return Reloc::PIC_;
196 if (!TT.isOSDarwin())
197 return Reloc::Static;
198 }
199
200 // If we are on Darwin, disallow static relocation model in X86-64 mode, since
201 // the Mach-O file format doesn't support it.
202 if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
203 return Reloc::PIC_;
204
205 return *RM;
206}
207
208static CodeModel::Model
209getEffectiveX86CodeModel(std::optional<CodeModel::Model> CM, bool JIT,
210 bool Is64Bit) {
211 if (CM) {
212 if (*CM == CodeModel::Tiny)
213 report_fatal_error("Target does not support the tiny CodeModel", false);
214 return *CM;
215 }
216 if (JIT)
217 return Is64Bit ? CodeModel::Large : CodeModel::Small;
218 return CodeModel::Small;
219}
220
221/// Create an X86 target.
222///
224 StringRef CPU, StringRef FS,
225 const TargetOptions &Options,
226 std::optional<Reloc::Model> RM,
227 std::optional<CodeModel::Model> CM,
228 CodeGenOptLevel OL, bool JIT)
230 T, computeDataLayout(TT), TT, CPU, FS, Options,
231 getEffectiveRelocModel(TT, JIT, RM),
232 getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
233 OL),
234 TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
235 // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
236 // the calling function, and TrapUnreachable is an easy way to get that.
237 if (TT.isPS() || TT.isOSBinFormatMachO()) {
238 this->Options.TrapUnreachable = true;
239 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
240 }
241
242 setMachineOutliner(true);
243
244 // x86 supports the debug entry values.
246
247 initAsmInfo();
248}
249
251
252const X86Subtarget *
254 Attribute CPUAttr = F.getFnAttribute("target-cpu");
255 Attribute TuneAttr = F.getFnAttribute("tune-cpu");
256 Attribute FSAttr = F.getFnAttribute("target-features");
257
258 StringRef CPU =
259 CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
260 // "x86-64" is a default target setting for many front ends. In these cases,
261 // they actually request for "generic" tuning unless the "tune-cpu" was
262 // specified.
263 StringRef TuneCPU = TuneAttr.isValid() ? TuneAttr.getValueAsString()
264 : CPU == "x86-64" ? "generic"
265 : (StringRef)CPU;
266 StringRef FS =
267 FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
268
270 // The additions here are ordered so that the definitely short strings are
271 // added first so we won't exceed the small size. We append the
272 // much longer FS string at the end so that we only heap allocate at most
273 // one time.
274
275 // Extract prefer-vector-width attribute.
276 unsigned PreferVectorWidthOverride = 0;
277 Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
278 if (PreferVecWidthAttr.isValid()) {
279 StringRef Val = PreferVecWidthAttr.getValueAsString();
280 unsigned Width;
281 if (!Val.getAsInteger(0, Width)) {
282 Key += 'p';
283 Key += Val;
284 PreferVectorWidthOverride = Width;
285 }
286 }
287
288 // Extract min-legal-vector-width attribute.
289 unsigned RequiredVectorWidth = UINT32_MAX;
290 Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
291 if (MinLegalVecWidthAttr.isValid()) {
292 StringRef Val = MinLegalVecWidthAttr.getValueAsString();
293 unsigned Width;
294 if (!Val.getAsInteger(0, Width)) {
295 Key += 'm';
296 Key += Val;
297 RequiredVectorWidth = Width;
298 }
299 }
300
301 // Add CPU to the Key.
302 Key += CPU;
303
304 // Add tune CPU to the Key.
305 Key += TuneCPU;
306
307 // Keep track of the start of the feature portion of the string.
308 unsigned FSStart = Key.size();
309
310 // FIXME: This is related to the code below to reset the target options,
311 // we need to know whether or not the soft float flag is set on the
312 // function before we can generate a subtarget. We also need to use
313 // it as a key for the subtarget since that can be the only difference
314 // between two functions.
315 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
316 // If the soft float attribute is set on the function turn on the soft float
317 // subtarget feature.
318 if (SoftFloat)
319 Key += FS.empty() ? "+soft-float" : "+soft-float,";
320
321 Key += FS;
322
323 // We may have added +soft-float to the features so move the StringRef to
324 // point to the full string in the Key.
325 FS = Key.substr(FSStart);
326
327 auto &I = SubtargetMap[Key];
328 if (!I) {
329 // This needs to be done before we create a new subtarget since any
330 // creation will depend on the TM and the code generation flags on the
331 // function that reside in TargetOptions.
333 I = std::make_unique<X86Subtarget>(
334 TargetTriple, CPU, TuneCPU, FS, *this,
335 MaybeAlign(F.getParent()->getOverrideStackAlignment()),
336 PreferVectorWidthOverride, RequiredVectorWidth);
337 }
338 return I.get();
339}
340
342 unsigned DestAS) const {
343 assert(SrcAS != DestAS && "Expected different address spaces!");
344 if (getPointerSize(SrcAS) != getPointerSize(DestAS))
345 return false;
346 return SrcAS < 256 && DestAS < 256;
347}
348
349//===----------------------------------------------------------------------===//
350// X86 TTI query.
351//===----------------------------------------------------------------------===//
352
355 return TargetTransformInfo(X86TTIImpl(this, F));
356}
357
358//===----------------------------------------------------------------------===//
359// Pass Pipeline Configuration
360//===----------------------------------------------------------------------===//
361
362namespace {
363
364/// X86 Code Generator Pass Configuration Options.
365class X86PassConfig : public TargetPassConfig {
366public:
367 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
368 : TargetPassConfig(TM, PM) {}
369
370 X86TargetMachine &getX86TargetMachine() const {
371 return getTM<X86TargetMachine>();
372 }
373
375 createMachineScheduler(MachineSchedContext *C) const override {
378 return DAG;
379 }
380
382 createPostMachineScheduler(MachineSchedContext *C) const override {
385 return DAG;
386 }
387
388 void addIRPasses() override;
389 bool addInstSelector() override;
390 bool addIRTranslator() override;
391 bool addLegalizeMachineIR() override;
392 bool addRegBankSelect() override;
393 bool addGlobalInstructionSelect() override;
394 bool addILPOpts() override;
395 bool addPreISel() override;
396 void addMachineSSAOptimization() override;
397 void addPreRegAlloc() override;
398 bool addPostFastRegAllocRewrite() override;
399 void addPostRegAlloc() override;
400 void addPreEmitPass() override;
401 void addPreEmitPass2() override;
402 void addPreSched2() override;
403 bool addRegAssignAndRewriteOptimized() override;
404
405 std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
406};
407
408class X86ExecutionDomainFix : public ExecutionDomainFix {
409public:
410 static char ID;
411 X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
412 StringRef getPassName() const override {
413 return "X86 Execution Dependency Fix";
414 }
415};
416char X86ExecutionDomainFix::ID;
417
418} // end anonymous namespace
419
420INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
421 "X86 Execution Domain Fix", false, false)
423INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
424 "X86 Execution Domain Fix", false, false)
425
427 return new X86PassConfig(*this, PM);
428}
429
431 BumpPtrAllocator &Allocator, const Function &F,
432 const TargetSubtargetInfo *STI) const {
433 return X86MachineFunctionInfo::create<X86MachineFunctionInfo>(Allocator, F,
434 STI);
435}
436
437void X86PassConfig::addIRPasses() {
438 addPass(createAtomicExpandPass());
439
440 // We add both pass anyway and when these two passes run, we skip the pass
441 // based on the option level and option attribute.
443 addPass(createX86LowerAMXTypePass());
444
446
447 if (TM->getOptLevel() != CodeGenOptLevel::None) {
450 }
451
452 // Add passes that handle indirect branch removal and insertion of a retpoline
453 // thunk. These will be a no-op unless a function subtarget has the retpoline
454 // feature enabled.
456
457 // Add Control Flow Guard checks.
458 const Triple &TT = TM->getTargetTriple();
459 if (TT.isOSWindows()) {
460 if (TT.getArch() == Triple::x86_64) {
461 addPass(createCFGuardDispatchPass());
462 } else {
463 addPass(createCFGuardCheckPass());
464 }
465 }
466
467 if (TM->Options.JMCInstrument)
468 addPass(createJMCInstrumenterPass());
469}
470
471bool X86PassConfig::addInstSelector() {
472 // Install an instruction selector.
473 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
474
475 // For ELF, cleanup any local-dynamic TLS accesses.
476 if (TM->getTargetTriple().isOSBinFormatELF() &&
477 getOptLevel() != CodeGenOptLevel::None)
479
482 return false;
483}
484
485bool X86PassConfig::addIRTranslator() {
486 addPass(new IRTranslator(getOptLevel()));
487 return false;
488}
489
490bool X86PassConfig::addLegalizeMachineIR() {
491 addPass(new Legalizer());
492 return false;
493}
494
495bool X86PassConfig::addRegBankSelect() {
496 addPass(new RegBankSelect());
497 return false;
498}
499
500bool X86PassConfig::addGlobalInstructionSelect() {
501 addPass(new InstructionSelect(getOptLevel()));
502 return false;
503}
504
505bool X86PassConfig::addILPOpts() {
506 addPass(&EarlyIfConverterID);
508 addPass(&MachineCombinerID);
510 return true;
511}
512
513bool X86PassConfig::addPreISel() {
514 // Only add this pass for 32-bit x86 Windows.
515 const Triple &TT = TM->getTargetTriple();
516 if (TT.isOSWindows() && TT.getArch() == Triple::x86)
517 addPass(createX86WinEHStatePass());
518 return true;
519}
520
521void X86PassConfig::addPreRegAlloc() {
522 if (getOptLevel() != CodeGenOptLevel::None) {
523 addPass(&LiveRangeShrinkID);
524 addPass(createX86FixupSetCC());
525 addPass(createX86OptimizeLEAs());
528 }
529
533
534 if (getOptLevel() != CodeGenOptLevel::None)
536 else
538}
539
540void X86PassConfig::addMachineSSAOptimization() {
543}
544
545void X86PassConfig::addPostRegAlloc() {
548 // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
549 // to using the Speculative Execution Side Effect Suppression pass for
550 // mitigation. This is to prevent slow downs due to
551 // analyses needed by the LVIHardening pass when compiling at -O0.
552 if (getOptLevel() != CodeGenOptLevel::None)
554}
555
556void X86PassConfig::addPreSched2() {
557 addPass(createX86ExpandPseudoPass());
558 addPass(createKCFIPass());
559}
560
561void X86PassConfig::addPreEmitPass() {
562 if (getOptLevel() != CodeGenOptLevel::None) {
563 addPass(new X86ExecutionDomainFix());
564 addPass(createBreakFalseDeps());
565 }
566
568
570
571 if (getOptLevel() != CodeGenOptLevel::None) {
572 addPass(createX86FixupBWInsts());
574 addPass(createX86FixupLEAs());
575 addPass(createX86FixupInstTuning());
577 }
578 addPass(createX86EvexToVexInsts());
582}
583
584void X86PassConfig::addPreEmitPass2() {
585 const Triple &TT = TM->getTargetTriple();
586 const MCAsmInfo *MAI = TM->getMCAsmInfo();
587
588 // The X86 Speculative Execution Pass must run after all control
589 // flow graph modifying passes. As a result it was listed to run right before
590 // the X86 Retpoline Thunks pass. The reason it must run after control flow
591 // graph modifications is that the model of LFENCE in LLVM has to be updated
592 // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
593 // placement of this pass was hand checked to ensure that the subsequent
594 // passes don't move the code around the LFENCEs in a way that will hurt the
595 // correctness of this pass. This placement has been shown to work based on
596 // hand inspection of the codegen output.
599 addPass(createX86ReturnThunksPass());
600
601 // Insert extra int3 instructions after trailing call instructions to avoid
602 // issues in the unwinder.
603 if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
605
606 // Verify basic block incoming and outgoing cfa offset and register values and
607 // correct CFA calculation rule where needed by inserting appropriate CFI
608 // instructions.
609 if (!TT.isOSDarwin() &&
610 (!TT.isOSWindows() ||
612 addPass(createCFIInstrInserter());
613
614 if (TT.isOSWindows()) {
615 // Identify valid longjmp targets for Windows Control Flow Guard.
616 addPass(createCFGuardLongjmpPass());
617 // Identify valid eh continuation targets for Windows EHCont Guard.
619 }
621
622 // Insert pseudo probe annotation for callsite profiling
623 addPass(createPseudoProbeInserter());
624
625 // KCFI indirect call checks are lowered to a bundle, and on Darwin platforms,
626 // also CALL_RVMARKER.
627 addPass(createUnpackMachineBundles([&TT](const MachineFunction &MF) {
628 // Only run bundle expansion if the module uses kcfi, or there are relevant
629 // ObjC runtime functions present in the module.
630 const Function &F = MF.getFunction();
631 const Module *M = F.getParent();
632 return M->getModuleFlag("kcfi") ||
633 (TT.isOSDarwin() &&
634 (M->getFunction("objc_retainAutoreleasedReturnValue") ||
635 M->getFunction("objc_unsafeClaimAutoreleasedReturnValue")));
636 }));
637}
638
639bool X86PassConfig::addPostFastRegAllocRewrite() {
641 return true;
642}
643
644std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
645 return getStandardCSEConfigForOpt(TM->getOptLevel());
646}
647
649 const TargetRegisterClass &RC) {
650 return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
651}
652
653bool X86PassConfig::addRegAssignAndRewriteOptimized() {
654 // Don't support tile RA when RA is specified by command line "-regalloc".
655 if (!isCustomizedRegAlloc() && EnableTileRAPass) {
656 // Allocate tile register first.
658 addPass(createX86TileConfigPass());
659 }
661}
Falkor HW Prefetch Fix
arm execution domain fix
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:135
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file declares the IRTranslator pass.
static LVOptions Options
Definition: LVOptions.cpp:25
static std::string computeDataLayout()
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
unsigned const TargetRegisterInfo * TRI
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
static cl::opt< bool > EnableMachineCombinerPass("ppc-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS_DEPENDENCY(depName)
Definition: PassSupport.h:55
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:59
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:52
Basic Register Allocator
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file contains some templates that are useful if you are working with the STL at all.
This file defines the SmallString class.
speculative execution
Target-Independent Code Generator Pass Configuration Options pass.
This pass exposes codegen information to IR-level passes.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(std::optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC)
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT, std::optional< Reloc::Model > RM)
This file a TargetTransformInfo::Concept conforming object specific to the X86 target machine.
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:318
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:184
Allocate memory in an ever growing pool, as if by bump-pointer.
Definition: Allocator.h:66
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:169
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class describes a target machine that is implemented with the LLVM target-independent code gener...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:787
Function & getFunction()
Return the LLVM function that this machine code represents.
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:37
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This class provides the reaching def analysis.
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:474
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:97
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::string TargetFS
Definition: TargetMachine.h:99
std::string TargetCPU
Definition: TargetMachine.h:98
std::unique_ptr< const MCSubtargetInfo > STI
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
@ DynamicNoPIC
Definition: CodeGen.h:25
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:445
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
FunctionPass * createIndirectBrExpandPass()
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
void initializeX86TileConfigPass(PassRegistry &)
void initializeX86PartialReductionPass(PassRegistry &)
void initializeX86CallFrameOptimizationPass(PassRegistry &)
void initializeFixupBWInstPassPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86ArgumentStackSlotPassPass(PassRegistry &)
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
void initializeWinEHStatePassPass(PassRegistry &)
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Target & getTheX86_32Target()
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
void initializeX86FastTileConfigPass(PassRegistry &)
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:306
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
Definition: CSEInfo.cpp:79
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
void initializeX86ExpandPseudoPass(PassRegistry &)
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
FunctionPass * createX86ArgumentStackSlotPass()
void initializeX86PreTileConfigPass(PassRegistry &)
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
void initializeX86DomainReassignmentPass(PassRegistry &)
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
void initializeX86AvoidSFBPassPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
void initializeX86FastPreTileConfigPass(PassRegistry &)
FunctionPass * createX86SpeculativeLoadHardeningPass()
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
void initializeX86FixupSetCCPassPass(PassRegistry &)
FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
Definition: KCFI.cpp:61
char & LiveRangeShrinkID
LiveRangeShrink pass.
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
void initializeEvexToVexInstPassPass(PassRegistry &)
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
FunctionPass * createX86FixupInstTuning()
Return a pass that replaces equivalent slower instructions with faster ones.
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
void initializeX86LowerTileCopyPass(PassRegistry &)
void initializeX86OptimizeLEAPassPass(PassRegistry &)
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
void initializeX86CmovConverterPassPass(PassRegistry &)
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
void initializeFPSPass(PassRegistry &)
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
void initializeKCFIPass(PassRegistry &)
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:302
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
void initializeX86DAGToDAGISelPass(PassRegistry &)
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
Target & getTheX86_64Target()
void initializePseudoProbeInserterPass(PassRegistry &)
FunctionPass * createX86FixupVectorConstants()
Return a pass that reduces the size of vector constant pool loads.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
FunctionPass * createX86ReturnThunksPass()
This pass replaces ret instructions with jmp's to __x86_return thunk.
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
void initializeX86ReturnThunksPass(PassRegistry &)
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
void initializeFixupLEAPassPass(PassRegistry &)
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
RegisterTargetMachine - Helper template for registering a target machine implementation,...