LLVM  15.0.0git
X86TargetMachine.cpp
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1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
38 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/IR/Attributes.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/TargetRegistry.h"
45 #include "llvm/Pass.h"
46 #include "llvm/Support/CodeGen.h"
52 #include <memory>
53 #include <string>
54 
55 using namespace llvm;
56 
57 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
58  cl::desc("Enable the machine combiner pass"),
59  cl::init(true), cl::Hidden);
60 
62  // Register the target.
65 
97 }
98 
99 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
100  if (TT.isOSBinFormatMachO()) {
101  if (TT.getArch() == Triple::x86_64)
102  return std::make_unique<X86_64MachoTargetObjectFile>();
103  return std::make_unique<TargetLoweringObjectFileMachO>();
104  }
105 
106  if (TT.isOSBinFormatCOFF())
107  return std::make_unique<TargetLoweringObjectFileCOFF>();
108  return std::make_unique<X86ELFTargetObjectFile>();
109 }
110 
111 static std::string computeDataLayout(const Triple &TT) {
112  // X86 is little endian
113  std::string Ret = "e";
114 
116  // X86 and x32 have 32 bit pointers.
117  if (!TT.isArch64Bit() || TT.isX32() || TT.isOSNaCl())
118  Ret += "-p:32:32";
119 
120  // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
121  Ret += "-p270:32:32-p271:32:32-p272:64:64";
122 
123  // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
124  if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
125  Ret += "-i64:64";
126  else if (TT.isOSIAMCU())
127  Ret += "-i64:32-f64:32";
128  else
129  Ret += "-f64:32:64";
130 
131  // Some ABIs align long double to 128 bits, others to 32.
132  if (TT.isOSNaCl() || TT.isOSIAMCU())
133  ; // No f80
134  else if (TT.isArch64Bit() || TT.isOSDarwin() || TT.isWindowsMSVCEnvironment())
135  Ret += "-f80:128";
136  else
137  Ret += "-f80:32";
138 
139  if (TT.isOSIAMCU())
140  Ret += "-f128:32";
141 
142  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
143  if (TT.isArch64Bit())
144  Ret += "-n8:16:32:64";
145  else
146  Ret += "-n8:16:32";
147 
148  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
149  if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
150  Ret += "-a:0:32-S32";
151  else
152  Ret += "-S128";
153 
154  return Ret;
155 }
156 
158  bool JIT,
160  bool is64Bit = TT.getArch() == Triple::x86_64;
161  if (!RM) {
162  // JIT codegen should use static relocations by default, since it's
163  // typically executed in process and not relocatable.
164  if (JIT)
165  return Reloc::Static;
166 
167  // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
168  // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
169  // use static relocation model by default.
170  if (TT.isOSDarwin()) {
171  if (is64Bit)
172  return Reloc::PIC_;
173  return Reloc::DynamicNoPIC;
174  }
175  if (TT.isOSWindows() && is64Bit)
176  return Reloc::PIC_;
177  return Reloc::Static;
178  }
179 
180  // ELF and X86-64 don't have a distinct DynamicNoPIC model. DynamicNoPIC
181  // is defined as a model for code which may be used in static or dynamic
182  // executables but not necessarily a shared library. On X86-32 we just
183  // compile in -static mode, in x86-64 we use PIC.
184  if (*RM == Reloc::DynamicNoPIC) {
185  if (is64Bit)
186  return Reloc::PIC_;
187  if (!TT.isOSDarwin())
188  return Reloc::Static;
189  }
190 
191  // If we are on Darwin, disallow static relocation model in X86-64 mode, since
192  // the Mach-O file format doesn't support it.
193  if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
194  return Reloc::PIC_;
195 
196  return *RM;
197 }
198 
200  bool JIT, bool Is64Bit) {
201  if (CM) {
202  if (*CM == CodeModel::Tiny)
203  report_fatal_error("Target does not support the tiny CodeModel", false);
204  return *CM;
205  }
206  if (JIT)
207  return Is64Bit ? CodeModel::Large : CodeModel::Small;
208  return CodeModel::Small;
209 }
210 
211 /// Create an X86 target.
212 ///
214  StringRef CPU, StringRef FS,
215  const TargetOptions &Options,
218  CodeGenOpt::Level OL, bool JIT)
220  T, computeDataLayout(TT), TT, CPU, FS, Options,
222  getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
223  OL),
224  TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
225  // On PS4/PS5, the "return address" of a 'noreturn' call must still be within
226  // the calling function, and TrapUnreachable is an easy way to get that.
227  if (TT.isPS() || TT.isOSBinFormatMachO()) {
228  this->Options.TrapUnreachable = true;
229  this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
230  }
231 
232  setMachineOutliner(true);
233 
234  // x86 supports the debug entry values.
236 
237  initAsmInfo();
238 }
239 
241 
242 const X86Subtarget *
244  Attribute CPUAttr = F.getFnAttribute("target-cpu");
245  Attribute TuneAttr = F.getFnAttribute("tune-cpu");
246  Attribute FSAttr = F.getFnAttribute("target-features");
247 
248  StringRef CPU =
249  CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
250  StringRef TuneCPU =
251  TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
252  StringRef FS =
253  FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
254 
256  // The additions here are ordered so that the definitely short strings are
257  // added first so we won't exceed the small size. We append the
258  // much longer FS string at the end so that we only heap allocate at most
259  // one time.
260 
261  // Extract prefer-vector-width attribute.
262  unsigned PreferVectorWidthOverride = 0;
263  Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
264  if (PreferVecWidthAttr.isValid()) {
265  StringRef Val = PreferVecWidthAttr.getValueAsString();
266  unsigned Width;
267  if (!Val.getAsInteger(0, Width)) {
268  Key += 'p';
269  Key += Val;
270  PreferVectorWidthOverride = Width;
271  }
272  }
273 
274  // Extract min-legal-vector-width attribute.
275  unsigned RequiredVectorWidth = UINT32_MAX;
276  Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
277  if (MinLegalVecWidthAttr.isValid()) {
278  StringRef Val = MinLegalVecWidthAttr.getValueAsString();
279  unsigned Width;
280  if (!Val.getAsInteger(0, Width)) {
281  Key += 'm';
282  Key += Val;
283  RequiredVectorWidth = Width;
284  }
285  }
286 
287  // Add CPU to the Key.
288  Key += CPU;
289 
290  // Add tune CPU to the Key.
291  Key += TuneCPU;
292 
293  // Keep track of the start of the feature portion of the string.
294  unsigned FSStart = Key.size();
295 
296  // FIXME: This is related to the code below to reset the target options,
297  // we need to know whether or not the soft float flag is set on the
298  // function before we can generate a subtarget. We also need to use
299  // it as a key for the subtarget since that can be the only difference
300  // between two functions.
301  bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool();
302  // If the soft float attribute is set on the function turn on the soft float
303  // subtarget feature.
304  if (SoftFloat)
305  Key += FS.empty() ? "+soft-float" : "+soft-float,";
306 
307  Key += FS;
308 
309  // We may have added +soft-float to the features so move the StringRef to
310  // point to the full string in the Key.
311  FS = Key.substr(FSStart);
312 
313  auto &I = SubtargetMap[Key];
314  if (!I) {
315  // This needs to be done before we create a new subtarget since any
316  // creation will depend on the TM and the code generation flags on the
317  // function that reside in TargetOptions.
319  I = std::make_unique<X86Subtarget>(
320  TargetTriple, CPU, TuneCPU, FS, *this,
321  MaybeAlign(F.getParent()->getOverrideStackAlignment()),
322  PreferVectorWidthOverride, RequiredVectorWidth);
323  }
324  return I.get();
325 }
326 
328  unsigned DestAS) const {
329  assert(SrcAS != DestAS && "Expected different address spaces!");
330  if (getPointerSize(SrcAS) != getPointerSize(DestAS))
331  return false;
332  return SrcAS < 256 && DestAS < 256;
333 }
334 
335 //===----------------------------------------------------------------------===//
336 // X86 TTI query.
337 //===----------------------------------------------------------------------===//
338 
341  return TargetTransformInfo(X86TTIImpl(this, F));
342 }
343 
344 //===----------------------------------------------------------------------===//
345 // Pass Pipeline Configuration
346 //===----------------------------------------------------------------------===//
347 
348 namespace {
349 
350 /// X86 Code Generator Pass Configuration Options.
351 class X86PassConfig : public TargetPassConfig {
352 public:
353  X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
354  : TargetPassConfig(TM, PM) {}
355 
356  X86TargetMachine &getX86TargetMachine() const {
357  return getTM<X86TargetMachine>();
358  }
359 
361  createMachineScheduler(MachineSchedContext *C) const override {
364  return DAG;
365  }
366 
368  createPostMachineScheduler(MachineSchedContext *C) const override {
371  return DAG;
372  }
373 
374  void addIRPasses() override;
375  bool addInstSelector() override;
376  bool addIRTranslator() override;
377  bool addLegalizeMachineIR() override;
378  bool addRegBankSelect() override;
379  bool addGlobalInstructionSelect() override;
380  bool addILPOpts() override;
381  bool addPreISel() override;
382  void addMachineSSAOptimization() override;
383  void addPreRegAlloc() override;
384  bool addPostFastRegAllocRewrite() override;
385  void addPostRegAlloc() override;
386  void addPreEmitPass() override;
387  void addPreEmitPass2() override;
388  void addPreSched2() override;
389  bool addPreRewrite() override;
390 
391  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
392 };
393 
394 class X86ExecutionDomainFix : public ExecutionDomainFix {
395 public:
396  static char ID;
397  X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
398  StringRef getPassName() const override {
399  return "X86 Execution Dependency Fix";
400  }
401 };
403 
404 } // end anonymous namespace
405 
406 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
407  "X86 Execution Domain Fix", false, false)
409 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
410  "X86 Execution Domain Fix", false, false)
411 
413  return new X86PassConfig(*this, PM);
414 }
415 
416 void X86PassConfig::addIRPasses() {
417  addPass(createAtomicExpandPass());
418 
419  // We add both pass anyway and when these two passes run, we skip the pass
420  // based on the option level and option attribute.
422  addPass(createX86LowerAMXTypePass());
423 
425 
426  if (TM->getOptLevel() != CodeGenOpt::None) {
427  addPass(createInterleavedAccessPass());
429  }
430 
431  // Add passes that handle indirect branch removal and insertion of a retpoline
432  // thunk. These will be a no-op unless a function subtarget has the retpoline
433  // feature enabled.
434  addPass(createIndirectBrExpandPass());
435 
436  // Add Control Flow Guard checks.
437  const Triple &TT = TM->getTargetTriple();
438  if (TT.isOSWindows()) {
439  if (TT.getArch() == Triple::x86_64) {
440  addPass(createCFGuardDispatchPass());
441  } else {
442  addPass(createCFGuardCheckPass());
443  }
444  }
445 
446  if (TM->Options.JMCInstrument)
447  addPass(createJMCInstrumenterPass());
448 }
449 
450 bool X86PassConfig::addInstSelector() {
451  // Install an instruction selector.
452  addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
453 
454  // For ELF, cleanup any local-dynamic TLS accesses.
455  if (TM->getTargetTriple().isOSBinFormatELF() &&
456  getOptLevel() != CodeGenOpt::None)
458 
459  addPass(createX86GlobalBaseRegPass());
460  return false;
461 }
462 
463 bool X86PassConfig::addIRTranslator() {
464  addPass(new IRTranslator(getOptLevel()));
465  return false;
466 }
467 
468 bool X86PassConfig::addLegalizeMachineIR() {
469  addPass(new Legalizer());
470  return false;
471 }
472 
473 bool X86PassConfig::addRegBankSelect() {
474  addPass(new RegBankSelect());
475  return false;
476 }
477 
478 bool X86PassConfig::addGlobalInstructionSelect() {
479  addPass(new InstructionSelect(getOptLevel()));
480  return false;
481 }
482 
483 bool X86PassConfig::addILPOpts() {
484  addPass(&EarlyIfConverterID);
486  addPass(&MachineCombinerID);
487  addPass(createX86CmovConverterPass());
488  return true;
489 }
490 
491 bool X86PassConfig::addPreISel() {
492  // Only add this pass for 32-bit x86 Windows.
493  const Triple &TT = TM->getTargetTriple();
494  if (TT.isOSWindows() && TT.getArch() == Triple::x86)
495  addPass(createX86WinEHStatePass());
496  return true;
497 }
498 
499 void X86PassConfig::addPreRegAlloc() {
500  if (getOptLevel() != CodeGenOpt::None) {
501  addPass(&LiveRangeShrinkID);
502  addPass(createX86FixupSetCC());
503  addPass(createX86OptimizeLEAs());
506  }
507 
510  addPass(createX86DynAllocaExpander());
511 
512  if (getOptLevel() != CodeGenOpt::None)
513  addPass(createX86PreTileConfigPass());
514  else
516 }
517 
518 void X86PassConfig::addMachineSSAOptimization() {
521 }
522 
523 void X86PassConfig::addPostRegAlloc() {
524  addPass(createX86LowerTileCopyPass());
526  // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
527  // to using the Speculative Execution Side Effect Suppression pass for
528  // mitigation. This is to prevent slow downs due to
529  // analyses needed by the LVIHardening pass when compiling at -O0.
530  if (getOptLevel() != CodeGenOpt::None)
532 }
533 
534 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
535 
536 void X86PassConfig::addPreEmitPass() {
537  if (getOptLevel() != CodeGenOpt::None) {
538  addPass(new X86ExecutionDomainFix());
539  addPass(createBreakFalseDeps());
540  }
541 
543 
544  addPass(createX86IssueVZeroUpperPass());
545 
546  if (getOptLevel() != CodeGenOpt::None) {
547  addPass(createX86FixupBWInsts());
548  addPass(createX86PadShortFunctions());
549  addPass(createX86FixupLEAs());
550  }
551  addPass(createX86EvexToVexInsts());
553  addPass(createX86InsertPrefetchPass());
554  addPass(createX86InsertX87waitPass());
555 }
556 
557 void X86PassConfig::addPreEmitPass2() {
558  const Triple &TT = TM->getTargetTriple();
559  const MCAsmInfo *MAI = TM->getMCAsmInfo();
560 
561  // The X86 Speculative Execution Pass must run after all control
562  // flow graph modifying passes. As a result it was listed to run right before
563  // the X86 Retpoline Thunks pass. The reason it must run after control flow
564  // graph modifications is that the model of LFENCE in LLVM has to be updated
565  // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
566  // placement of this pass was hand checked to ensure that the subsequent
567  // passes don't move the code around the LFENCEs in a way that will hurt the
568  // correctness of this pass. This placement has been shown to work based on
569  // hand inspection of the codegen output.
571  addPass(createX86IndirectThunksPass());
572 
573  // Insert extra int3 instructions after trailing call instructions to avoid
574  // issues in the unwinder.
575  if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
577 
578  // Verify basic block incoming and outgoing cfa offset and register values and
579  // correct CFA calculation rule where needed by inserting appropriate CFI
580  // instructions.
581  if (!TT.isOSDarwin() &&
582  (!TT.isOSWindows() ||
584  addPass(createCFIInstrInserter());
585 
586  if (TT.isOSWindows()) {
587  // Identify valid longjmp targets for Windows Control Flow Guard.
588  addPass(createCFGuardLongjmpPass());
589  // Identify valid eh continuation targets for Windows EHCont Guard.
591  }
593 
594  // Insert pseudo probe annotation for callsite profiling
595  addPass(createPseudoProbeInserter());
596 
597  // On Darwin platforms, BLR_RVMARKER pseudo instructions are lowered to
598  // bundles.
599  if (TT.isOSDarwin())
600  addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
601  // Only run bundle expansion if there are relevant ObjC runtime functions
602  // present in the module.
603  const Function &F = MF.getFunction();
604  const Module *M = F.getParent();
605  return M->getFunction("objc_retainAutoreleasedReturnValue") ||
606  M->getFunction("objc_unsafeClaimAutoreleasedReturnValue");
607  }));
608 }
609 
610 bool X86PassConfig::addPostFastRegAllocRewrite() {
611  addPass(createX86FastTileConfigPass());
612  return true;
613 }
614 
615 bool X86PassConfig::addPreRewrite() {
616  addPass(createX86TileConfigPass());
617  return true;
618 }
619 
620 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
621  return getStandardCSEConfigForOpt(TM->getOptLevel());
622 }
llvm::createX86LowerAMXTypePass
FunctionPass * createX86LowerAMXTypePass()
The pass transforms load/store <256 x i32> to AMX load/store intrinsics or split the data to two <128...
Definition: X86LowerAMXType.cpp:1245
llvm::createJMCInstrumenterPass
ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
llvm::createX86FlagsCopyLoweringPass
FunctionPass * createX86FlagsCopyLoweringPass()
Return a pass that lowers EFLAGS copy pseudo instructions.
Definition: X86FlagsCopyLowering.cpp:140
llvm::createX86FixupLEAs
FunctionPass * createX86FixupLEAs()
Return a pass that selectively replaces certain instructions (like add, sub, inc, dec,...
Definition: X86FixupLEAs.cpp:218
llvm::createX86PadShortFunctions
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
Definition: X86PadShortFunction.cpp:99
llvm
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:17
llvm::Attribute::isValid
bool isValid() const
Return true if the attribute is any kind of attribute.
Definition: Attributes.h:182
M
We currently emits eax Perhaps this is what we really should generate is Is imull three or four cycles eax eax The current instruction priority is based on pattern complexity The former is more complex because it folds a load so the latter will not be emitted Perhaps we should use AddedComplexity to give LEA32r a higher priority We should always try to match LEA first since the LEA matching code does some estimate to determine whether the match is profitable if we care more about code then imull is better It s two bytes shorter than movl leal On a Pentium M
Definition: README.txt:252
llvm::createX86DynAllocaExpander
FunctionPass * createX86DynAllocaExpander()
Return a pass that expands DynAlloca pseudo-instructions.
Definition: X86DynAllocaExpander.cpp:75
Optional.h
llvm::ARM::PredBlockMask::TT
@ TT
X86CallLowering.h
llvm::X86TargetMachine::getTargetTransformInfo
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
Definition: X86TargetMachine.cpp:340
llvm::createX86AvoidTrailingCallPass
FunctionPass * createX86AvoidTrailingCallPass()
Return a pass that inserts int3 at the end of the function if it ends with a CALL instruction.
Definition: X86AvoidTrailingCall.cpp:64
llvm::ReachingDefAnalysis
This class provides the reaching def analysis.
Definition: ReachingDefAnalysis.h:69
llvm::initializeX86FastPreTileConfigPass
void initializeX86FastPreTileConfigPass(PassRegistry &)
CallLowering.h
X86Subtarget.h
llvm::TargetOptions
Definition: TargetOptions.h:124
T
llvm::Function
Definition: Function.h:60
llvm::Attribute
Definition: Attributes.h:65
StringRef.h
Pass.h
llvm::getTheX86_64Target
Target & getTheX86_64Target()
Definition: X86TargetInfo.cpp:17
is64Bit
static bool is64Bit(const char *name)
Definition: X86Disassembler.cpp:1018
llvm::initializeX86FastTileConfigPass
void initializeX86FastTileConfigPass(PassRegistry &)
llvm::Triple::x86
@ x86
Definition: Triple.h:85
llvm::createX86PreTileConfigPass
FunctionPass * createX86PreTileConfigPass()
Return a pass that insert pseudo tile config instruction.
Definition: X86PreTileConfig.cpp:412
llvm::MCAsmInfo
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
llvm::Target
Target - Wrapper for Target specific information.
Definition: TargetRegistry.h:145
llvm::initializeEvexToVexInstPassPass
void initializeEvexToVexInstPassPass(PassRegistry &)
llvm::X86Subtarget
Definition: X86Subtarget.h:52
ErrorHandling.h
llvm::TargetTransformInfo
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
Definition: TargetTransformInfo.h:168
llvm::createX86IndirectThunksPass
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
Definition: X86IndirectThunks.cpp:255
llvm::X86TargetMachine::X86TargetMachine
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
Create an X86 target.
Definition: X86TargetMachine.cpp:213
llvm::Triple
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
llvm::cl::Hidden
@ Hidden
Definition: CommandLine.h:139
llvm::Triple::x86_64
@ x86_64
Definition: Triple.h:86
llvm::DataLayout::getManglingComponent
static const char * getManglingComponent(const Triple &T)
Definition: DataLayout.cpp:153
llvm::TargetOptions::TrapUnreachable
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
Definition: TargetOptions.h:280
InstructionSelect.h
llvm::initializeX86ExpandPseudoPass
void initializeX86ExpandPseudoPass(PassRegistry &)
llvm::createCleanupLocalDynamicTLSPass
FunctionPass * createCleanupLocalDynamicTLSPass()
This pass combines multiple accesses to local-dynamic TLS variables so that the TLS base address for ...
Definition: X86InstrInfo.cpp:9466
llvm::Optional< Reloc::Model >
llvm::initializeGlobalISel
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:17
llvm::ExecutionDomainFix
Definition: ExecutionDomainFix.h:116
getEffectiveX86CodeModel
static CodeModel::Model getEffectiveX86CodeModel(Optional< CodeModel::Model > CM, bool JIT, bool Is64Bit)
Definition: X86TargetMachine.cpp:199
llvm::MipsISD::Ret
@ Ret
Definition: MipsISelLowering.h:119
STLExtras.h
llvm::createX86TileConfigPass
FunctionPass * createX86TileConfigPass()
Return a pass that config the tile registers.
Definition: X86TileConfig.cpp:199
llvm::createX86FixupSetCC
FunctionPass * createX86FixupSetCC()
Return a pass that transforms setcc + movzx pairs into xor + setcc.
Definition: X86FixupSetCC.cpp:59
F
#define F(x, y, z)
Definition: MD5.cpp:55
llvm::createX86FastTileConfigPass
FunctionPass * createX86FastTileConfigPass()
Return a pass that config the tile registers after fast reg allocation.
Definition: X86FastTileConfig.cpp:186
llvm::Reloc::Model
Model
Definition: CodeGen.h:22
CSEInfo.h
llvm::createX86MacroFusionDAGMutation
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86PassConfig::crea...
Definition: X86MacroFusion.cpp:71
CommandLine.h
X86.h
llvm::createX86CallFrameOptimization
FunctionPass * createX86CallFrameOptimization()
Return a pass that optimizes the code-size of x86 call sequences.
Definition: X86CallFrameOptimization.cpp:638
fix
x86 execution domain fix
Definition: X86TargetMachine.cpp:409
llvm::createEHContGuardCatchretPass
FunctionPass * createEHContGuardCatchretPass()
Creates EHContGuard catchret target identification pass.
llvm::PassRegistry::getPassRegistry
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Definition: PassRegistry.cpp:31
llvm::X86TargetMachine::isNoopAddrSpaceCast
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Definition: X86TargetMachine.cpp:327
X86MacroFusion.h
llvm::createX86FloatingPointStackifierPass
FunctionPass * createX86FloatingPointStackifierPass()
This function returns a pass which converts floating-point register references and pseudo instruction...
Definition: X86FloatingPoint.cpp:311
SmallString.h
llvm::TargetMachine::setMachineOutliner
void setMachineOutliner(bool Enable)
Definition: TargetMachine.h:250
Fix
x86 execution domain X86 Execution Domain Fix
Definition: X86TargetMachine.cpp:410
llvm::Legalizer
Definition: Legalizer.h:36
C
(vector float) vec_cmpeq(*A, *B) C
Definition: README_ALTIVEC.txt:86
Y
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
llvm::createX86SpeculativeLoadHardeningPass
FunctionPass * createX86SpeculativeLoadHardeningPass()
Definition: X86SpeculativeLoadHardening.cpp:2276
Domain
Domain
Definition: CorrelatedValuePropagation.cpp:710
llvm::AMDGPU::PALMD::Key
Key
PAL metadata keys.
Definition: AMDGPUMetadata.h:486
false
Definition: StackSlotColoring.cpp:141
llvm::EarlyIfConverterID
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
Definition: EarlyIfConversion.cpp:782
llvm::MaybeAlign
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Definition: Alignment.h:117
llvm::createX86PartialReductionPass
FunctionPass * createX86PartialReductionPass()
This pass optimizes arithmetic based on knowledge that is only used by a reduction sequence and is th...
Definition: X86PartialReduction.cpp:60
llvm::createGenericSchedPostRA
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Definition: MachineScheduler.cpp:3646
llvm::CodeModel::Small
@ Small
Definition: CodeGen.h:28
llvm::createAtomicExpandPass
FunctionPass * createAtomicExpandPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
llvm::InstructionSelect
This pass is responsible for selecting generic machine instructions to target-specific instructions.
Definition: InstructionSelect.h:33
llvm::RegisterTargetMachine
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Definition: TargetRegistry.h:1318
llvm::ScheduleDAGMI::addMutation
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
Definition: MachineScheduler.h:323
llvm::createX86LowerAMXIntrinsicsPass
FunctionPass * createX86LowerAMXIntrinsicsPass()
The pass transforms amx intrinsics to scalar operation if the function has optnone attribute or it is...
Definition: X86LowerAMXIntrinsics.cpp:679
llvm::PassRegistry
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
Definition: PassRegistry.h:38
llvm::createCFIInstrInserter
FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
llvm::createCFGuardDispatchPass
FunctionPass * createCFGuardDispatchPass()
Insert Control FLow Guard dispatches on indirect function calls.
Definition: CFGuard.cpp:304
llvm::report_fatal_error
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:143
Options
const char LLVMTargetMachineRef LLVMPassBuilderOptionsRef Options
Definition: PassBuilderBindings.cpp:48
llvm::initializePseudoProbeInserterPass
void initializePseudoProbeInserterPass(PassRegistry &)
llvm::initializeX86SpeculativeLoadHardeningPassPass
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &)
llvm::initializeWinEHStatePassPass
void initializeWinEHStatePassPass(PassRegistry &)
llvm::TargetMachine::TargetFS
std::string TargetFS
Definition: TargetMachine.h:98
llvm::Attribute::getValueAsString
StringRef getValueAsString() const
Return the attribute's value as a string.
Definition: Attributes.cpp:304
llvm::StringRef::getAsInteger
std::enable_if_t< std::numeric_limits< T >::is_signed, bool > getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:514
llvm::createX86LowerTileCopyPass
FunctionPass * createX86LowerTileCopyPass()
Return a pass that lower the tile copy instruction.
Definition: X86LowerTileCopy.cpp:68
llvm::CallingConv::ID
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
X
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
llvm::TargetMachine::resetTargetOptions
void resetTargetOptions(const Function &F) const
Reset the target options based on the function's attributes.
Definition: TargetMachine.cpp:53
llvm::SmallString
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
INITIALIZE_PASS_END
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
Definition: PassSupport.h:58
llvm::createX86LoadValueInjectionRetHardeningPass
FunctionPass * createX86LoadValueInjectionRetHardeningPass()
llvm::CodeModel::Model
Model
Definition: CodeGen.h:28
Passes.h
llvm::TargetPassConfig
Target-Independent Code Generator Pass Configuration Options.
Definition: TargetPassConfig.h:84
InstructionSelector.h
llvm::createX86SpeculativeExecutionSideEffectSuppression
FunctionPass * createX86SpeculativeExecutionSideEffectSuppression()
Definition: X86SpeculativeExecutionSideEffectSuppression.cpp:176
llvm::cl::opt< bool >
llvm::initializeX86LoadValueInjectionRetHardeningPassPass
void initializeX86LoadValueInjectionRetHardeningPassPass(PassRegistry &)
llvm::TargetMachine::TargetTriple
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
Definition: TargetMachine.h:96
llvm::getTheX86_32Target
Target & getTheX86_32Target()
Definition: X86TargetInfo.cpp:13
llvm::createX86DiscriminateMemOpsPass
FunctionPass * createX86DiscriminateMemOpsPass()
This pass ensures instructions featuring a memory operand have distinctive <LineNumber,...
Definition: X86DiscriminateMemOps.cpp:183
X86MCTargetDesc.h
llvm::createX86WinEHStatePass
FunctionPass * createX86WinEHStatePass()
Return an IR pass that inserts EH registration stack objects and explicit EH state updates.
Definition: X86WinEHState.cpp:114
llvm::initializeFPSPass
void initializeFPSPass(PassRegistry &)
CFGuard.h
llvm::createGenericSchedLive
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
Definition: MachineScheduler.cpp:3489
llvm::EngineKind::JIT
@ JIT
Definition: ExecutionEngine.h:524
LLVM_EXTERNAL_VISIBILITY
#define LLVM_EXTERNAL_VISIBILITY
Definition: Compiler.h:126
INITIALIZE_PASS_DEPENDENCY
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
X86LegalizerInfo.h
llvm::createX86DomainReassignmentPass
FunctionPass * createX86DomainReassignmentPass()
Return a Machine IR pass that reassigns instruction chains from one domain to another,...
LLVMInitializeX86Target
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target()
Definition: X86TargetMachine.cpp:61
llvm::MachineSchedContext
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
Definition: MachineScheduler.h:125
llvm::TargetOptions::NoTrapAfterNoreturn
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
Definition: TargetOptions.h:284
I
#define I(x, y, z)
Definition: MD5.cpp:58
llvm::createX86InsertPrefetchPass
FunctionPass * createX86InsertPrefetchPass()
This pass applies profiling information to insert cache prefetches.
Definition: X86InsertPrefetch.cpp:252
llvm::TargetPassConfig::addIRPasses
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
Definition: TargetPassConfig.cpp:853
llvm::createUnpackMachineBundles
FunctionPass * createUnpackMachineBundles(std::function< bool(const MachineFunction &)> Ftor)
Definition: MachineInstrBundle.cpp:81
llvm::createX86AvoidStoreForwardingBlocks
FunctionPass * createX86AvoidStoreForwardingBlocks()
Return a pass that avoids creating store forward block issues in the hardware.
Definition: X86AvoidStoreForwardingBlocks.cpp:129
llvm::cl::init
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
llvm::createX86ISelDag
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
Definition: X86ISelDAGToDAG.cpp:6192
llvm::LiveRangeShrinkID
char & LiveRangeShrinkID
LiveRangeShrink pass.
Definition: LiveRangeShrink.cpp:64
TargetPassConfig.h
llvm::initializeX86LowerAMXTypeLegacyPassPass
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
assert
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
llvm::X86AS::FS
@ FS
Definition: X86.h:192
llvm::initializeX86AvoidTrailingCallPassPass
void initializeX86AvoidTrailingCallPassPass(PassRegistry &)
llvm::X86TargetMachine
Definition: X86TargetMachine.h:28
llvm::createCFGuardCheckPass
FunctionPass * createCFGuardCheckPass()
Insert Control FLow Guard checks on indirect function calls.
Definition: CFGuard.cpp:300
llvm::createX86ExpandPseudoPass
FunctionPass * createX86ExpandPseudoPass()
Return a Machine IR pass that expands X86-specific pseudo instructions into a sequence of actual inst...
Definition: X86ExpandPseudo.cpp:747
llvm::Module
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
llvm::ScheduleDAGMI
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
Definition: MachineScheduler.h:271
llvm::createX86FixupBWInsts
FunctionPass * createX86FixupBWInsts()
Return a Machine IR pass that selectively replaces certain byte and word instructions by equivalent 3...
Definition: X86FixupBWInsts.cpp:159
llvm::initializeX86LowerTileCopyPass
void initializeX86LowerTileCopyPass(PassRegistry &)
llvm::Reloc::DynamicNoPIC
@ DynamicNoPIC
Definition: CodeGen.h:22
llvm::MachineFunction
Definition: MachineFunction.h:257
llvm::X86TargetMachine::getSubtargetImpl
const X86Subtarget * getSubtargetImpl() const =delete
Triple.h
INITIALIZE_PASS_BEGIN
INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix", "X86 Execution Domain Fix", false, false) INITIALIZE_PASS_END(X86ExecutionDomainFix
llvm::CodeGenOpt::None
@ None
Definition: CodeGen.h:53
TargetOptions.h
llvm::AArch64::RM
@ RM
Definition: AArch64ISelLowering.h:469
MCAsmInfo.h
llvm::Reloc::PIC_
@ PIC_
Definition: CodeGen.h:22
DataLayout.h
llvm::StringRef
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:58
X86TargetTransformInfo.h
TargetLoweringObjectFile.h
llvm::Reloc::Static
@ Static
Definition: CodeGen.h:22
llvm::getStandardCSEConfigForOpt
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:75
IRTranslator.h
EnableMachineCombinerPass
static cl::opt< bool > EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
llvm::createIndirectBrExpandPass
FunctionPass * createIndirectBrExpandPass()
Definition: IndirectBrExpandPass.cpp:77
llvm::CodeGenOpt::Level
Level
Definition: CodeGen.h:52
llvm::CodeModel::Tiny
@ Tiny
Definition: CodeGen.h:28
llvm::getEffectiveRelocModel
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
Definition: AVRTargetMachine.cpp:40
llvm::LLVMTargetMachine::initAsmInfo
void initAsmInfo()
Definition: LLVMTargetMachine.cpp:40
llvm::createInterleavedAccessPass
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Definition: InterleavedAccessPass.cpp:145
llvm::createX86LoadValueInjectionLoadHardeningPass
FunctionPass * createX86LoadValueInjectionLoadHardeningPass()
Definition: X86LoadValueInjectionLoadHardening.cpp:814
Attributes.h
llvm::createBreakFalseDeps
FunctionPass * createBreakFalseDeps()
Creates Break False Dependencies pass.
Definition: BreakFalseDeps.cpp:107
llvm::X86TTIImpl
Definition: X86TargetTransformInfo.h:27
llvm::createX86EvexToVexInsts
FunctionPass * createX86EvexToVexInsts()
This pass replaces EVEX encoded of AVX-512 instructiosn by VEX encoding when possible in order to red...
Definition: X86EvexToVex.cpp:278
llvm::initializeFixupBWInstPassPass
void initializeFixupBWInstPassPass(PassRegistry &)
llvm::MachineFunction::getFunction
Function & getFunction()
Return the LLVM function that this machine code represents.
Definition: MachineFunction.h:622
llvm::initializeFixupLEAPassPass
void initializeFixupLEAPassPass(PassRegistry &)
computeDataLayout
static std::string computeDataLayout(const Triple &TT)
Definition: X86TargetMachine.cpp:111
X86TargetMachine.h
llvm::initializeX86LowerAMXIntrinsicsLegacyPassPass
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
llvm::TargetPassConfig::addMachineSSAOptimization
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
Definition: TargetPassConfig.cpp:1306
X86TargetObjectFile.h
RegBankSelect.h
Function.h
createTLOF
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Definition: X86TargetMachine.cpp:99
llvm::createPseudoProbeInserter
FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
Definition: PseudoProbeInserter.cpp:151
llvm::initializeX86PreTileConfigPass
void initializeX86PreTileConfigPass(PassRegistry &)
llvm::createX86InsertX87waitPass
FunctionPass * createX86InsertX87waitPass()
This pass insert wait instruction after X87 instructions which could raise fp exceptions when strict-...
Definition: X86InsertWait.cpp:56
llvm::LLVMTargetMachine
This class describes a target machine that is implemented with the LLVM target-independent code gener...
Definition: TargetMachine.h:411
llvm::initializeX86SpeculativeExecutionSideEffectSuppressionPass
void initializeX86SpeculativeExecutionSideEffectSuppressionPass(PassRegistry &)
llvm::createX86FastPreTileConfigPass
FunctionPass * createX86FastPreTileConfigPass()
Return a pass that preconfig the tile registers before fast reg allocation.
Definition: X86FastPreTileConfig.cpp:707
llvm::initializeX86TileConfigPass
void initializeX86TileConfigPass(PassRegistry &)
llvm::AMDGPU::Hwreg::Width
Width
Definition: SIDefines.h:436
llvm::initializeX86LoadValueInjectionLoadHardeningPassPass
void initializeX86LoadValueInjectionLoadHardeningPassPass(PassRegistry &)
llvm::initializeX86CallFrameOptimizationPass
void initializeX86CallFrameOptimizationPass(PassRegistry &)
CodeGen.h
llvm::MCAsmInfo::getExceptionHandlingType
ExceptionHandling getExceptionHandlingType() const
Definition: MCAsmInfo.h:777
ExecutionDomainFix.h
llvm::CodeModel::Large
@ Large
Definition: CodeGen.h:28
Legalizer.h
MachineScheduler.h
llvm::initializeX86PartialReductionPass
void initializeX86PartialReductionPass(PassRegistry &)
llvm::initializeX86FixupSetCCPassPass
void initializeX86FixupSetCCPassPass(PassRegistry &)
llvm::createX86CmovConverterPass
FunctionPass * createX86CmovConverterPass()
This pass converts X86 cmov instructions into branch when profitable.
Definition: X86CmovConversion.cpp:873
llvm::createX86IndirectBranchTrackingPass
FunctionPass * createX86IndirectBranchTrackingPass()
This pass inserts ENDBR instructions before indirect jump/call destinations as part of CET IBT mechan...
Definition: X86IndirectBranchTracking.cpp:68
llvm::MachineCombinerID
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Definition: MachineCombiner.cpp:129
TargetTransformInfo.h
llvm::initializeX86AvoidSFBPassPass
void initializeX86AvoidSFBPassPass(PassRegistry &)
llvm::legacy::PassManagerBase
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
Definition: LegacyPassManager.h:39
llvm::IRTranslator
Definition: IRTranslator.h:62
llvm::initializeX86OptimizeLEAPassPass
void initializeX86OptimizeLEAPassPass(PassRegistry &)
llvm::initializeX86ExecutionDomainFixPass
void initializeX86ExecutionDomainFixPass(PassRegistry &)
TM
const char LLVMTargetMachineRef TM
Definition: PassBuilderBindings.cpp:47
llvm::createX86GlobalBaseRegPass
FunctionPass * createX86GlobalBaseRegPass()
This pass initializes a global base register for PIC on x86-32.
Definition: X86InstrInfo.cpp:9352
llvm::X86TargetMachine::~X86TargetMachine
~X86TargetMachine() override
llvm::RegBankSelect
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
llvm::createX86OptimizeLEAs
FunctionPass * createX86OptimizeLEAs()
Return a pass that removes redundant LEA instructions and redundant address recalculations.
Definition: X86OptimizeLEAs.cpp:315
llvm::TargetMachine::setSupportsDebugEntryValues
void setSupportsDebugEntryValues(bool Enable)
Definition: TargetMachine.h:256
llvm::initializeX86DomainReassignmentPass
void initializeX86DomainReassignmentPass(PassRegistry &)
llvm::cl::desc
Definition: CommandLine.h:405
llvm::ScheduleDAGMILive
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
Definition: MachineScheduler.h:390
execution
speculative execution
Definition: SpeculativeExecution.cpp:135
llvm::initializeX86FlagsCopyLoweringPassPass
void initializeX86FlagsCopyLoweringPassPass(PassRegistry &)
llvm::createX86IssueVZeroUpperPass
FunctionPass * createX86IssueVZeroUpperPass()
This pass inserts AVX vzeroupper instructions before each call to avoid transition penalty between fu...
Definition: X86VZeroUpper.cpp:116
llvm::ScheduleDAGInstrs
A ScheduleDAG for scheduling lists of MachineInstr.
Definition: ScheduleDAGInstrs.h:119
llvm::TargetMachine::getPointerSize
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
Definition: TargetMachine.h:183
X86
Unrolling by would eliminate the &in both leading to a net reduction in code size The resultant code would then also be suitable for exit value computation We miss a bunch of rotate opportunities on various including etc On X86
Definition: README.txt:568
X86TargetInfo.h
TargetRegistry.h
llvm::ExceptionHandling::DwarfCFI
@ DwarfCFI
DWARF-like instruction based exceptions.
llvm::TargetMachine::TargetCPU
std::string TargetCPU
Definition: TargetMachine.h:97
llvm::initializeX86PreAMXConfigPassPass
void initializeX86PreAMXConfigPassPass(PassRegistry &)
llvm::initializeX86CmovConverterPassPass
void initializeX86CmovConverterPassPass(PassRegistry &)
llvm::createCFGuardLongjmpPass
FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
llvm::Intrinsic::ID
unsigned ID
Definition: TargetTransformInfo.h:38